Compressed scan collar architecture for asynchronous finite state machines

A method of implementing a scan collar architecture for testing an asynchronous finite state machine (AFSM), the method comprising:

• identifying states of the AFSM;
• generating an evolution matrix representing relationships between the states and state transition arcs of the AFSM;
• determining compatibility between states based on the evolution matrix, wherein states are compatible in response to having no direct transition relationship between them;
• allocating compatible states to shared output test registers of the scan collar architecture;
• and
• monitoring state transitions through the shared output test registers.

A design for test (DFT) architecture for an asynchronous finite state machine (AFSM), comprising:

• a compressed input circuit including:
• a plurality of shared input test registers;
• a plurality of multiplexers coupled to the shared input test registers;
• and
• input routing logic configured to allocate compatible functional signals to shared input test registers in response to corresponding state transitions having different source states and in response to a destination state of one state transition not being a source state of another state transition;
• a compressed output circuit including:
• a plurality of shared output test registers;
• a plurality of logic gates coupled to the shared output test registers;
• and
• output routing logic configured to allocate compatible state signals to shared output test registers in response to corresponding states having no direct transition relationship;
• and
• an AFSM core coupled between the compressed input circuit and the compressed output circuit.