US 5,036,473 AGranted

Method of using electronically reconfigurable logic circuits

AssigneeMentor Graphics Corporation

InventorsMichael R. Butts, Jon A. Batcheller

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Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims19

Dependent claims

A method comprising the steps:

providing first and second electrically reconfigurable logic circuits (ERCLCs);
providing first input data representative of a first digital logic network, said input data including primitives comprised of boolean logic gates, and nets interconnecting said primitives;
automatically partitioning said first input data into first and second portions;
providing the first portion of the partitioned first data to the first ERCLC so a first portion of the first digital logic network represented thereby takes actual operating form on the first ERCLC;
providing the second portion of the partitioned first data to the second ERCLC so a second portion of the first digital logic network represented thereby takes actual operating form on the second ERCLC;
interconnecting the first and second ERCLCs so that at least one net specified in the first input data extends between the first and second ERCLCs;
providing second input data representative of a second digital logic network entirely unrelated to the first digital logic network except that both include primitives comprised of boolean logic gates, and nets interconnecting said primitives, and both are to take actual operating form on the same ERCLCs;
automatically partitioning said second input data into first and second portions;
providing the first portion of the partitioned second data to the first ERCLC so a first portion of the second digital logic network represented thereby takes actual operating form on the first ERCLC;
providing the second portion of the partitioned second data to the second ERCLC so a second portion of the second digital logic network represented thereby takes actual operating form on the second ERCLC;
interconnecting the first and second ERCLCs so that at least one net specified in the second input data extends between the first and second ERCLCs.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/417,196Filed 4 Oct 1989 · continuation in part
Priority: 5 Oct 1988
Granted: 30 Jul 1991
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 15/7867
Comprising a single central processing unit: with reconfigurable architecture
G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing