G06F 30/327
Logic synthesis
Official title: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F30/327 (Logic synthesis) appears on 3,173 US grants and 2,653 published applications in this corpus.
Search patents in G06F- Granted patents
- 3,173
- Published applications
- 2,653
- Assignees
- 621
- Inventors
- 5,642
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 2 | 0 |
| 1988 | 0 | 0 |
| 1989 | 4 | 0 |
| 1990 | 4 | 0 |
| 1991 | 5 | 0 |
| 1992 | 7 | 0 |
| 1993 | 10 | 0 |
| 1994 | 9 | 0 |
| 1995 | 21 | 0 |
| 1996 | 14 | 0 |
| 1997 | 19 | 0 |
| 1998 | 25 | 0 |
| 1999 | 29 | 0 |
| 2000 | 26 | 0 |
| 2001 | 40 | 22 |
| 2002 | 60 | 49 |
| 2003 | 67 | 65 |
| 2004 | 49 | 67 |
| 2005 | 54 | 60 |
| 2006 | 78 | 88 |
| 2007 | 67 | 66 |
| 2008 | 76 | 89 |
| 2009 | 78 | 102 |
| 2010 | 89 | 78 |
| 2011 | 120 | 80 |
| 2012 | 130 | 123 |
| 2013 | 180 | 102 |
| 2014 | 166 | 120 |
| 2015 | 173 | 124 |
| 2016 | 148 | 148 |
| 2017 | 172 | 150 |
| 2018 | 122 | 164 |
| 2019 | 215 | 176 |
| 2020 | 274 | 131 |
| 2021 | 155 | 106 |
| 2022 | 90 | 110 |
| 2023 | 150 | 134 |
| 2024 | 87 | 122 |
| 2025 | 92 | 96 |
| 2026 | 66 | 81 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Compiling a tensor tiling specification to multi-dimensional data mover circuit configurations6 Oct 2026US 12,755,077 B2Xilinx, Inc.
- Methods and apparatus to automate a design including routing between dice6 Oct 2026US 12,755,080 B2Intel Corporation
- Machine learning for netlist design15 Sep 2026US 12,737,518 B2QUALCOMM Incorporated
- Incremental synthesis from RTL circuit designs in EDA15 Sep 2026US 12,737,526 B1Cadence Design Systems, Inc.
- System and method for electronic circuit emulation8 Sep 2026US 12,730,949 B2
- Circuit topology synthesis using large language models and reinforcement learning8 Oct 2026US 2026/0310867 A1International Business Machines Corporation
- Logical time division multiplexing of digital logic designs1 Oct 2026US 2026/0300592 A1VeriSilicon Holdings Co., Ltd.
- Synthesis of register transfer level (rtl) code to identify changes to the rtl code to improve a performance metric10 Sep 2026US 2026/0268051 A1Microchip Technology Incorporated
- Circuit Implementation on Processing Circuitry10 Sep 2026US 2026/0268052 A1Altera Corporation
- Programmable Input And Output Interfaces In Processing Integrated Circuits For Servers And Other Devices10 Sep 2026US 2026/0268053 A1Altera Corporation
Most cited
By later US patents
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995
- Method and apparatus for designing circuits for wave pipelining258US 5,796,624 AThe Research Foundation of State University of New York · 1998
- Method for storing multiple levels of design data in a common database229US 6,505,328 B1Magma Design Automation, Inc. · 2003
- Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries229US 6,523,156 B2Library Technologies, Inc. · 2003
- Integrated circuit design with delayed cell selection228US 6,275,973 B1LSI Logic Corporation · 2001