Logical time division multiplexing of digital logic designs
AssigneesVeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
InventorJen-Te Lee
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AssigneesVeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
InventorJen-Te Lee
Estimating the term…
N instances of a design including stateless combinational logic and data storage, e.g., flip-flops, are replaced with a logically time-division multiplexed (TDM) design including a single instance of the combinational logic and N instances of the data storage chained together such that for all but the first instance, an instance will receive the output of a preceding instance. The N instances of the data storage are driven by a sub-divided clock that generates N clock cycles for each clock cycle of an external clock. The output of the last instance is input to the combinational logic and the first instance receives an output of the combinational logic. A bridging circuit serializes input data and deserializes the outputs of the combinational logic for each clock cycle of the sub-divided clock. A single RAM instance of the design may likewise be modified for use in the TDM design.
A method comprising:
A non-transitory computer-readable medium storing executable code that, when executed by one or more processing devices, causes the one or more processing devices to:
An apparatus comprising:
Dependencies are inferred from the claim text.