Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries

A computer readable medium for generating an integrated circuit (IC) layout design, the computer readable medium comprising:

• computer readable code for providing an initial layout netlist having a plurality of original cells;
• computer readable code for replacing a first original cell within the initial layout netlist with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as the first original cell when the first original cell is not optimal, wherein the first replacement delay of a particular cell is the particular cell's total delay contribution to a particular delay path that includes the particular cell;
• and
• a computer readable medium for storing the computer readable codes,
• wherein the first replacement is prior to any routing procedure being performed on the layout netlist, wherein the first replacement cell is capable of driving the first original cell's load, excluding a wire load that is associated with the first original cell and is introduced by a subsequent routing procedure, the first original cell not being optimal when it is incapable of driving its own load, excluding the wire load,
• the replacement of the first original cell comprising:
• determining a total input gate capacitance of the first original cell excluding the wire load;
• selecting the first replacement cell from a plurality of possible replacement cells, wherein the selection is made based on which replacement cell is capable of driving a load at least as large as the determined total input gate capacitance;
• and
• replacing the first original cell with the selected first replacement cell.