Method and apparatus for designing circuits for wave pipelining
AssigneeThe Research Foundation of State University of New York
InventorsRamalingam Sridhar, Zhang Xuguang
Life of this patent
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Abstract
A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.
Claims28
A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps:
- forming a map of the desired logic function;
- assigning cells of the map into pairs of map cells;
- implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value;
- implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal;
- and
- adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern.
A method for designing a wave-pipelining circuit, the wave-pipelining circuit including a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps:
- forming a map of the desired logic function;
- assigning cells of the map into pairs of cells;
- implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value, and for each transmission gate, if any,
- coupling a first terminal to a first input signal,
- coupling a second terminal to a node, and
- coupling a gate to a second input signal;
- implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal, and for each pull transistor, if any,
- coupling a first terminal to a voltage source,
- coupling a second terminal to the node, and
- coupling a gate to a third input signal;
- implementing a driver coupled to the node, the driver amplifying a signal, adjusting logic levels, and providing an output signal;
- and
- adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern for each one of a plurality of paths to the output signal from the first input signal, the second input signal and the third input signal, respectively, each one of the paths passing through the driver and one or more of the transmission gate and the pull transistor.
A method for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the method comprising the steps:
- determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate;
- and
- determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
A system for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the system comprising:
- means for determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate;
- and
- means for determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
Dependencies are inferred from the claim text.