Mask optimization for layer accounting for overlap with other layers
AssigneeD2S, Inc.
InventorsDonald Oriordan, Akira Fujimura
Life of this patent
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Abstract
Some embodiments provide a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC). The method generates, based on a first mask layout, a simulated wafer image having predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC. The method identifies a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC. The first and second IC components are related components in the IC. Based on the cross-sectional overlap, the method modifies the first mask layout to generate a modified second mask layout for the first layer.
Claims20
A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
- generating, based on a mask layout for a first layer of the IC, a plurality of simulated wafer images, each respective simulated wafer image comprising respective predicted manufactured shapes representing IC components that are to be manufactured on the first layer of the IC accounting for a respective set of manufacturing process variations;
- identifying a cross-sectional overlap between a first shape of a first IC component in at least one of the simulated wafer images and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC, wherein the sets of manufacturing process variations comprise (i) wafer misalignment variations that result in misalignment between the first and second layers and (ii) manufactured size variations that result in the first and second shapes having different sizes;
- and
- based on the cross-sectional overlap, modifying the first mask layout to generate a modified mask layout for the first layer.
A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
- generating, based on a mask layout for a first layer of the IC, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on the first layer of the IC;
- identifying (i) a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC and (ii) a cross-sectional overlap between a third shape of a third IC component in the simulated wafer image and a fourth shape of a fourth IC component in a wafer image for a third layer of the IC, wherein the first and second IC components are related components in the IC and the third and fourth IC components are related components in the IC;
- and
- modifying the mask layout for the first layer to generate a modified mask layout for the first layer by optimizing the mask layout based on (i) the identified overlap between the first and second shapes and (ii) the identified overlap between the third and fourth shapes.
A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
- generating, based on a mask layout for a first layer of the IC, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on the first layer of the IC;
- identifying (i) a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC and (ii) a cross-sectional overlap between the first shape and a third shape of a third IC component in a wafer image for a third layer of the IC, wherein the first and second IC components are related components in the IC and the first and third IC components are related components in the IC;
- and
- modifying the mask layout for the first layer to generate a modified mask layout for the first layer by optimizing the mask layout based on (i) the identified overlap between the first and second shapes and (ii) the identified overlap between the first and third shapes.
A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout generated from a design layout of an integrated circuit (IC), the program comprising sets of instructions for:
- generating, based on a mask layout for a first layer of the IC, a plurality of simulated wafer images, each respective simulated wafer image comprising respective predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC accounting for a respective set of manufacturing process variations;
- identifying a cross-sectional overlap between a first shape of a first IC component in at least one of the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC, wherein the sets of manufacturing process variations comprise (i) wafer misalignment variations that result in misalignment between the first and second layers and (ii) manufactured size variations that result in the first and second shapes having different sizes;
- and
- based on the cross-sectional overlap, modifying the first mask layout to generate a modified mask layout for the first layer.
Dependencies are inferred from the claim text.