Mask optimization for layer based on comparison of components in layer to components in other layers
AssigneeD2S, Inc.
InventorsDonald Oriordan, Akira Fujimura
Life of this patent
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AssigneeD2S, Inc.
InventorsDonald Oriordan, Akira Fujimura
Estimating the term…
Some embodiments provide a method for optimizing a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate. The method generates, based on a first mask layout, a simulated wafer image including representations of IC components that are predicted to be manufactured for a first layer of the IC based on a received mask layout for the first layer. The method compares the simulated wafer image to a target wafer image including optimal representations of the IC components for the first layer. The comparison uses data regarding locations of components in at least one additional layer that interact with components in the first layer. Based on the comparison, the method modifies the first mask layout to generate a modified second mask layout for the first layer.
A method for optimizing a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate, the method comprising:
A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate, the program comprising sets of instructions for:
Dependencies are inferred from the claim text.