US 2026/0310067 A1 · MASK OPTIMIZATION ACCOUNTING FOR MORE CRITICAL AND LESS CRITICAL OVERLAP REGIONS

Abstract

Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing components of the first layer, including a first component that overlaps with a second component on a second layer. The method identifies a more critical first region and a less critical second region of a first shape of the first component that both overlap with a second shape of the second component. The more critical first region is more important to ensuring overlap of the first shape with the second shape. To improve overlap between the first and second shapes, the method uses different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout.

Claims20

Dependent claims

A method for optimizing a mask layout for a first layer of a design layout for an integrated circuit (IC), the method comprising:

iteratively:
based on a current mask layout for the first layer, generating a simulated wafer image comprising shapes that represent IC components of the first layer;
in the simulated wafer image, identifying first and second regions of a first shape of a first IC component in the first layer, the first and second regions both overlapping with a second shape of a second IC component in a second layer;
and
using different first and second costs respectively for the overlaps of the first and second regions with the second shape to modify the current mask layout to produce a modified mask layout;
and
after a plurality of iterations, defining a mask layout for manufacturing a mask to use to fabricate the first layer of the IC.

4 more elements

A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for a first layer of a design layout for an integrated circuit (IC), the program comprising sets of instructions for:

iteratively:
based on a current mask layout for the first layer, generating a simulated wafer image comprising shapes that represent IC components of the first layer;
in the simulated wafer image, identifying first and second regions of a first shape of a first IC component in the first layer, the first and second regions both overlapping with a second shape of a second IC component in a second layer;
and
using different first and second costs respectively for the overlaps of the first and second regions with the second shape to modify the current mask layout to produce a modified mask layout;
and
after a plurality of iterations, defining a mask layout for manufacturing a mask to use to fabricate the first layer of the IC.

4 more elements

Dependencies are inferred from the claim text.

Mask optimization accounting for more critical and less critical overlap regions

Life of this patent

Mask optimization accounting for more critical and less critical overlap regions

Life of this patent

Abstract

Claims20