G06F 30/35
Delay-insensitive circuit design
Official title: Delay-insensitive circuit design, e.g. asynchronous or self-timed
G06F30/35 (Delay-insensitive circuit design) appears on 161 US grants and 162 published applications in this corpus.
Search patents in G06F- Granted patents
- 161
- Published applications
- 162
- Assignees
- 87
- Inventors
- 308
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 2 | 0 |
| 2002 | 0 | 2 |
| 2003 | 3 | 3 |
| 2004 | 3 | 3 |
| 2005 | 2 | 5 |
| 2006 | 0 | 8 |
| 2007 | 2 | 3 |
| 2008 | 5 | 3 |
| 2009 | 3 | 15 |
| 2010 | 7 | 5 |
| 2011 | 11 | 5 |
| 2012 | 7 | 7 |
| 2013 | 12 | 9 |
| 2014 | 10 | 9 |
| 2015 | 3 | 18 |
| 2016 | 7 | 10 |
| 2017 | 17 | 10 |
| 2018 | 7 | 7 |
| 2019 | 23 | 17 |
| 2020 | 10 | 7 |
| 2021 | 9 | 3 |
| 2022 | 2 | 0 |
| 2023 | 4 | 3 |
| 2024 | 2 | 3 |
| 2025 | 1 | 5 |
| 2026 | 1 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Intra-package memory die communication structures25 Aug 2026US 12,718,865 B2Micron Technology, Inc.
- System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design28 Jan 2025US 12,210,810 B2Arteris, Inc.
- Reduced-power dynamic data circuits with wide-band energy recovery26 Nov 2024US 12,153,867 B2Rezonent Corporation
- Intra-package memory die communication structures18 Jun 2024US 12,014,765 B2Micron Technology, Inc.
- Reduced-power dynamic data circuits with wide-band energy recovery19 Sep 2023US 11,763,055 B2Rezonent Corporation
- Asynchronous finite state machine circuit, corresponding method of operation and integrated circuit18 Jun 2026US 2026/0169762 A1STMicroelectronics International N. V.
- Method for generating circuit design for asynchronous circuit, automated asynchronous circuit design tool, and asynchronous circuit29 Jan 2026US 2026/0030427 A1Renesas Design (UK) Limited
- Area efficient asynchronous circuit generator25 Sep 2025US 2025/0298949 A1University of Cincinnati
- Circuit quality confirmation apparatus and circuit quality confirmation method3 Jul 2025US 2025/0217564 A1Mitsubishi Electric Corporation
- System and method for training a neural learning model for predicting performance, power and area behavior of ip components in integrated circuit design29 May 2025US 2025/0173490 A1Arteris, Inc.
Most cited
By later US patents
- Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same350US 5,867,691 AKabushiki Kaisha Toshiba · 1999
- Optimization of cell subtypes in a hierarchical design flow214US 6,854,096 B2Fulcrum Microsystems, Inc. · 2005
- Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits73US 5,469,367 AUniversity Technologies International Inc. · 1995
- Zero overhead self-timed iterative logic50US 5,121,003 AHaL Computer Systems, Inc. · 1992
- Asynchronous processors48US 5,752,070 ACalifornia Institute of Technology · 1998