Circuit quality confirmation apparatus and circuit quality confirmation method

A circuit quality confirmation apparatus comprising:

• processing circuitry to:
• calculate, using a dedicated timing constraint that indicates an upper limit of a wiring delay value of an asynchronous clock interface path in an embedded circuit in which a dedicated circuit that is an asynchronous clock interface circuit where an input/output waveform of a signal is uniquely defined in accordance with a timing condition that is set and that is an asynchronous clock interface circuit that includes an asynchronous clock interface path is embedded, a worst condition that is a timing condition that is a theoretical limit of data that can be taken in in a subsequent stage of the asynchronous clock interface path in the embedded circuit, and that is a timing condition that is calculated based on a wiring delay that is expected to occur in a post-layout netlist equivalent to a circuit that is generated by executing a layout corresponding to the embedded circuit, and delay time that occurs by at least one of a phase relationship between asynchronous clocks, a clock jitter, a clock skew, a setup time, and a hold time in the dedicated circuit, and
• validate quality of the embedded circuit by executing a validation tool that statically validates the quality of the embedded circuit using the embedded circuit, a timing constraint of the embedded circuit, and a worst condition that is calculated, wherein
• each of the dedicated circuit that is the asynchronous clock interface circuit and the embedded circuit is a circuit expressed by a hardware description language.