Intra-package memory die communication structures
AssigneeMicron Technology, Inc.
InventorHari Giduturi
Life of this patent
Estimating the term…
Abstract
A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.
Claims20
A system comprising:
- a packaged memory device including multiple memory dies coupled using a shared bus, the dies including:
- a first die coupled to a host interface and a shared bus;
- a second die coupled to the shared bus, wherein the second die corresponds to a first chip identifier;
- and
- a third die coupled to the shared bus, wherein the third die corresponds to a second chip identifier;
- wherein the first die is configured to use a selected one of the first chip identifier and the second chip identifier to communicate, via the shared bus, with the corresponding one of the second die and the third die, and wherein when the first die communicates a first message with the first chip identifier using the shared bus, the third die is configured to disregard information on the shared bus.
A system comprising:
- a packaged memory device coupled to a host device using a host interface, wherein the packaged memory device comprises multiple memory dies coupled using a shared bus, the multiple memory dies including:
- a first die coupled to the host interface and the shared bus;
- a second die coupled to the shared bus, wherein the second die is uniquely identified by a first identifier;
- and
- a third die coupled to the shared bus, wherein the third die is uniquely identified by a second identifier;
- wherein the first die is configured to communicate, via the shared bus, a first message to the second die and the third die, and wherein when the first message comprises an identification field with the first identifier, the second die is configured to receive read and/or write messages from the first die.
A packaged memory device comprising:
- a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus;
- and
- multiple secondary dies coupled to the intra-package communication bus and decoupled from the host interface bus, wherein each of the secondary dies is configured to receive the same messages from the primary memory die using the intra-package communication bus;
- and
- wherein each of the secondary dies has a respective die-specific identifier and each of the secondary dies comprises respective logic circuitry configured to compare information from a die identification field in each of the messages to the die-specific identifier and determine whether to respond to each of the messages from the primary memory die, wherein a first one of the secondary dies corresponds to a first die-specific identifier and a second one of the secondary dies corresponds to a second die-specific identifier, wherein when the primary memory die communicates a first message comprising the die identification field with the first die-specific identifier using the intra-package communication bus, the first one of the secondary dies is configured to receive read and/or write messages from the primary memory die, and the second one of the secondary dies is configured to disregard information on the intra-package communication bus.
Dependencies are inferred from the claim text.