Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same

An inter-hierarchy synchronizing system comprising:

• a higher-level functional hardware block for generating input event generation signals in accordance with a timing relation in a higher-level timing system in which timings are expressed by higher-level timing variables;
• a lower-level functional hardware block, arranged in a hierarchical structure in combination with said higher-level functional hardware block, for performing predetermined operations in accordance with a local timing relation in a local timing system in which timings are expressed by a local timing variable that is not necessarily coincident with said higher-level timing variables on the basis of activation signals, wherein requirements of said system are functionally decomposed into said lower-level and higher-level functional hardware blocks;
• and
• an inter-hierarchy synchronizing means, provided between said higher-level functional hardware block and said lower-level functional hardware block, for outputting said activation signals for activating said lower-level functional hardware block by said local timing system on the basis of said input event generation signals generated by said higher-level functional hardware block, supplying said activation signals to said lower-level functional hardware block, generating a task completion signal at said higher-level timing system when an output event generation signal generated from said lower-level functional hardware block is set to indicate that all tasks are completed by said lower-level functional hardware block, and supplying said task completion signal to said higher-level functional hardware block,
• wherein said system is arranged in a hierarchical structure in which said higher-level functional hardware block controls a plurality of lower-level functional hardware blocks each having a local timing system, and said inter-hierarchy synchronizing means activates said plurality of lower-level functional hardware blocks in parallel.