Method of and device for generating layout diagram

A method of generating a via layout diagram of a layout plan of a semiconductor device prior to application of an optical proximity correction (OPC) process, comprising:

• obtaining an initial layout plan that includes
• a first layout pattern included in a first metallization layout diagram and indicative of a first conductive structure,
• a second layout pattern included in a second metallization layout diagram and indicative of a second conductive structure, and
• an initial via layout pattern included in an initial via layout diagram and indicative of electrically coupling of the first conductive structure and the second conductive structure;
• deriving a first estimated pattern based on the first layout pattern;
• deriving a second estimated pattern based on the second layout pattern;
• determining a modified via layout pattern based on the first estimated pattern and the second estimated pattern, the modified via layout pattern indicative of a via structure of the semiconductor device connecting the first conductive structure under the via structure and the second conductive structure over the via structure;
• and
• saving, to a memory device of a processing device, the via layout diagram of the layout plan that corresponds to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern,
• wherein
• the modified via layout pattern has a curved shape prior to the application of the OPC process.

A processing device for generating a via layout diagram of a layout plan of a semiconductor device prior to application of an optical proximity correction (OPC) process, comprising:

• a memory device;
• and
• processing circuitry coupled to the memory device and configured to:
• obtain an initial layout plan that includes
• a first layout pattern included in a first metallization layout diagram and indicative of a first conductive structure,
• a second layout pattern included in a second metallization layout diagram and indicative of a second conductive structure, and
• an initial via layout pattern included in an initial via layout diagram and indicative of electrically coupling of the first conductive structure and the second conductive structure;
• derive a first estimated pattern based on the first layout pattern;
• derive a second estimated pattern based on the second layout pattern;
• determine a modified via layout pattern based on the first estimated pattern and the second estimated pattern, the modified via layout pattern indicative of a via structure of the semiconductor device connecting the first conductive structure under the via structure and the second conductive structure over the via structure;
• and
• save, to the memory device, the via layout diagram of the layout plan that corresponds to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern,
• wherein
• the modified via layout pattern has a curved shape prior to the application of the OPC process.