Three dimensional memory in a system on a chip
OwnerNeal Solomoninventor
Life of this patent
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Abstract
The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.
Claims20
A multi-planar memory system consisting of a plurality of memory circuit planes in a three dimensional (3D) stem on a chip (SoC) with through silicon vias (TSVs) comprised of:
- a multi-circuit set of memory circuit layers arranged in a 3D configuration;
- a plurality of memory circuit layers, each layer of which includes memory circuit component types;
- at least one logic circuit layer connected to the memory circuit layers by TSVs;
- wherein the types of memory on memory circuit layers are used by at least one logic circuit layer, which are configured to access at least one memory type on each memory circuit layer using the TSVs;
- wherein when at least one memory type on a memory circuit layer is sandwiched between at least two logic circuit layers, the memory types on the memory circuit layers are connected with TSVs;
- and
- wherein the memory circuit layers store data and instructions.
A multi-planar memory system consisting of a plurality of memory circuit planes in three dimensional (3D) system on a chip (SoC) with through silicon vias (TSVs) comprised of:
- a multi-circuit set of memory circuit layers arranged in a 3D configuration;
- a plurality of memory circuit layers, each layer of which includes memory circuit component types;
- at least one logic circuit layer configured to access at least one memory circuit layer by TSVs;
- wherein the types of memory in the memory circuit layers are used by at least one logic circuit layer, which are configured to access at least one memory type on each memory circuit layer using the TSVs;
- wherein when at least one memory type on a memory circuit layer is sandwiched between at least two logic circuit layers, the memory types on the memory circuit layers are connected with TSVs;
- wherein at least one logic circuit layer accesses different memory types on the memory circuit layers in the 3D SoC simultaneously;
- and
- wherein the memory circuit layers store data and instructions.
A multi-planar memory system consisting of a plurality of memory circuit planes in a three dimensional (3D) memory module with through silicon vias (TSVs) comprised of:
- a multi-circuit set of memory circuit layers arranged in a 3D configuration;
- a plurality of memory circuit layers, each layer of which includes memory circuit component types;
- at least one logic circuit configured to access and control at least one memory circuit, such logic circuit on at least one tile of a layer of the multi-layer memory system;
- wherein the multi-planar memory system is configured as a set of memory types on memory circuit layers in an integrated memory module connected with TSVs;
- wherein at least one logic circuit on a tile on one layer in the 3D memory module accesses data and instructions from the memory types in at least one memory circuit layer using the TSVs;
- and
- wherein the memory circuits on at least one layer of the 3D memory module store data and instructions.
Dependencies are inferred from the claim text.