G06F 30/36
Circuit design at the analogue level
G06F30/36 (Circuit design at the analogue level) appears on 4,556 US grants and 4,414 published applications in this corpus.
Search patents in G06F- Granted patents
- 4,556
- Published applications
- 4,414
- Assignees
- 1,140
- Inventors
- 9,129
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 2 | 0 |
| 1989 | 4 | 0 |
| 1990 | 4 | 0 |
| 1991 | 5 | 0 |
| 1992 | 5 | 0 |
| 1993 | 6 | 0 |
| 1994 | 12 | 0 |
| 1995 | 12 | 0 |
| 1996 | 17 | 0 |
| 1997 | 24 | 0 |
| 1998 | 24 | 0 |
| 1999 | 35 | 0 |
| 2000 | 41 | 0 |
| 2001 | 60 | 12 |
| 2002 | 70 | 105 |
| 2003 | 127 | 152 |
| 2004 | 112 | 171 |
| 2005 | 115 | 142 |
| 2006 | 150 | 159 |
| 2007 | 125 | 143 |
| 2008 | 135 | 200 |
| 2009 | 124 | 197 |
| 2010 | 154 | 169 |
| 2011 | 180 | 143 |
| 2012 | 224 | 153 |
| 2013 | 235 | 200 |
| 2014 | 270 | 210 |
| 2015 | 205 | 206 |
| 2016 | 166 | 196 |
| 2017 | 202 | 232 |
| 2018 | 177 | 211 |
| 2019 | 290 | 173 |
| 2020 | 278 | 198 |
| 2021 | 206 | 192 |
| 2022 | 180 | 203 |
| 2023 | 181 | 203 |
| 2024 | 133 | 184 |
| 2025 | 156 | 164 |
| 2026 | 104 | 96 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Mask optimization for layer accounting for overlap with other layers6 Oct 2026US 12,754,471 B2D2S, Inc.
- Mask optimization for layer based on comparison of components in layer to components in other layers6 Oct 2026US 12,754,472 B2D2S, Inc.
- Mask optimization preferentially accounting for overlap regions6 Oct 2026US 12,754,473 B2D2S, Inc.
- Concurrent mask optimization for multiple layers6 Oct 2026US 12,754,474 B2D2S, Inc.
- Helper assertion guidance for circuit design verification6 Oct 2026US 12,755,078 B1Cadence Design Systems, Inc.
- Mask optimization accounting for more critical and less critical overlap regions8 Oct 2026US 2026/0310067 A1D2S, Inc.
- Solving system, training method and solving method for partial differential equations of electric field of integrated circuit device1 Oct 2026US 2026/0300430 A1Huazhong University of Science and Technology
- Electronic device, computer-readable storage medium and method for extracting parasitic capacitance of interconnect lines of integrated circuit1 Oct 2026US 2026/0300594 A1Huazhong University of Science and Technology
- Early-Stage Integrated Circuit Electrostatic Discharge Safeguarding17 Sep 2026US 2026/0278231 A1Google Inc.
- Integrated routing assembly and system using same17 Sep 2026US 2026/0278238 A1Molex Incorporated
Most cited
By later US patents
- Parasitic capacitance extraction for FinFETs436US 8,826,213 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Design-manufacturing interface via a unified model287US 7,155,689 B2Magma Design Automation, Inc. · 2006
- Method for verification of crosstalk noise in a CMOS design251US 6,499,131 B1Texas Instruments Incorporated · 2002
- Gate-length biasing for digital circuit optimization245US 7,441,211 B1Blaze Dfm, Inc. · 2008
- Deep sub-micron static timing analysis in the presence of crosstalk244US 6,405,348 B1Synopsys, Inc. · 2002