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US 7,155,689 B2Granted
Design-manufacturing interface via a unified model
AssigneeMagma Design Automation, Inc.
InventorsChristophe Pierrat, Alfred K. Wong
Life of this patent
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AssigneeMagma Design Automation, Inc.
InventorsChristophe Pierrat, Alfred K. Wong
Estimating the term…
Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.
A method for obtaining a layout description for a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for verifying a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for identifying weak spots in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for defining a physical connection in a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for compacting a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for layout synthesis of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for generating a design rule used in the generation of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for extracting an electrical parameter from a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for interactive layout editing of a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for modifying a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for disposing of an anomaly of a mask fabricated using a layout of a target patterned layer of material in an integrated circuit including a plurality of patterned layers of material, comprising:
A method for manufacturing an integrated circuit including a plurality of patterned layers of material, said integrated circuit including at least one target patterned layer of material, comprising:
Dependencies are inferred from the claim text.