G06F 30/367
Design verification
Official title: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F30/367 (Design verification) appears on 3,982 US grants and 3,819 published applications in this corpus.
Search patents in G06F- Granted patents
- 3,982
- Published applications
- 3,819
- Assignees
- 1,001
- Inventors
- 7,992
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 2 | 0 |
| 1989 | 4 | 0 |
| 1990 | 3 | 0 |
| 1991 | 4 | 0 |
| 1992 | 5 | 0 |
| 1993 | 5 | 0 |
| 1994 | 11 | 0 |
| 1995 | 11 | 0 |
| 1996 | 16 | 0 |
| 1997 | 24 | 0 |
| 1998 | 24 | 0 |
| 1999 | 33 | 0 |
| 2000 | 41 | 0 |
| 2001 | 53 | 10 |
| 2002 | 68 | 98 |
| 2003 | 119 | 143 |
| 2004 | 104 | 149 |
| 2005 | 102 | 134 |
| 2006 | 132 | 151 |
| 2007 | 118 | 134 |
| 2008 | 126 | 177 |
| 2009 | 116 | 178 |
| 2010 | 136 | 147 |
| 2011 | 165 | 129 |
| 2012 | 204 | 138 |
| 2013 | 206 | 160 |
| 2014 | 229 | 178 |
| 2015 | 174 | 167 |
| 2016 | 135 | 161 |
| 2017 | 170 | 202 |
| 2018 | 147 | 181 |
| 2019 | 252 | 147 |
| 2020 | 241 | 162 |
| 2021 | 169 | 160 |
| 2022 | 151 | 157 |
| 2023 | 152 | 175 |
| 2024 | 112 | 157 |
| 2025 | 131 | 135 |
| 2026 | 84 | 89 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Mask optimization for layer accounting for overlap with other layers6 Oct 2026US 12,754,471 B2D2S, Inc.
- Mask optimization for layer based on comparison of components in layer to components in other layers6 Oct 2026US 12,754,472 B2D2S, Inc.
- Mask optimization preferentially accounting for overlap regions6 Oct 2026US 12,754,473 B2D2S, Inc.
- Concurrent mask optimization for multiple layers6 Oct 2026US 12,754,474 B2D2S, Inc.
- Helper assertion guidance for circuit design verification6 Oct 2026US 12,755,078 B1Cadence Design Systems, Inc.
- Mask optimization accounting for more critical and less critical overlap regions8 Oct 2026US 2026/0310067 A1D2S, Inc.
- Solving system, training method and solving method for partial differential equations of electric field of integrated circuit device1 Oct 2026US 2026/0300430 A1Huazhong University of Science and Technology
- Electronic device, computer-readable storage medium and method for extracting parasitic capacitance of interconnect lines of integrated circuit1 Oct 2026US 2026/0300594 A1Huazhong University of Science and Technology
- Early-Stage Integrated Circuit Electrostatic Discharge Safeguarding17 Sep 2026US 2026/0278231 A1Google Inc.
- Integrated routing assembly and system using same17 Sep 2026US 2026/0278238 A1Molex Incorporated
Most cited
By later US patents
- Parasitic capacitance extraction for FinFETs436US 8,826,213 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Design-manufacturing interface via a unified model287US 7,155,689 B2Magma Design Automation, Inc. · 2006
- Method for verification of crosstalk noise in a CMOS design251US 6,499,131 B1Texas Instruments Incorporated · 2002
- Deep sub-micron static timing analysis in the presence of crosstalk244US 6,405,348 B1Synopsys, Inc. · 2002
- Method of simulation for gate oxide integrity check on an entire IC243US 6,378,109 B1Texas Instruments Incorporated · 2002