Early-Stage Integrated Circuit Electrostatic Discharge Safeguarding
AssigneeGoogle Inc.
InventorsVaibhav Gupta, Sandeep Nachireddy
Life of this patent
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Abstract
The present disclosure describes techniques and apparatuses that are directed to integrated circuit design and fabrication. Designers may, for example, apply the techniques to identify failing Electrostatic Discharge (ESD) clamps at a floor planning stage, rather than waiting for signoff. These techniques, including a new flow process, may successfully identify violations missed by traditional flow processes, and may identify such violations earlier in the overall design and fabrication process.
Claims20
A method for verifying electrostatic discharge (ESD) protection in an integrated circuit design, the method comprising:
- receiving a layout of the integrated circuit design during an early design phase, the layout including at least one ESD protection circuit and not being required to be short-clean;
- configuring a grid-based extraction tool to model an internal structure of the at least one ESD protection circuit from an upper metal layer down to a lower metal layer;
- modeling layers of the integrated circuit design by modeling the internal structure of the at least one ESD protection circuit while excluding unrelated power grid geometries that do not impact ESD analysis;
- analyzing a resistance, a current density, or both of the at least one ESD protection circuit using the configured grid-based extraction tool to identify violations within the internal structure;
- and
- generating a verification report indicating whether the at least one ESD protection circuit meets a robustness threshold defined for the lower metal layer.
An apparatus for verifying electrostatic discharge (ESD) protection in an integrated circuit (IC) design, the apparatus comprising:
- a memory storing a layout of the integrated circuit design, the layout including at least one ESD protection circuit;
- and
- a processor coupled to the memory and configured to execute a grid-based extraction tool configured to:
- model an internal structure of the at least one ESD protection circuit from an upper metal layer down to a lower metal layer during an early design phase, the layout of the IC design not required to be short-clean;
- extract geometries by including layers of the internal structure of the at least one ESD protection circuit and excluding unrelated power grid geometries;
- calculate resistance and current density through the internal structure of the at least one ESD protection circuit;
- and
- verify the at least one ESD protection circuit against a robustness threshold associated with the lower metal layer.
Dependencies are inferred from the claim text.