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US 7,441,211 B1Granted
Gate-length biasing for digital circuit optimization
AssigneeBlaze Dfm, Inc.
InventorsPuneet Gupta, Andrew B Kahng
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Abstract
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.
Claims36
A gate-length biasing method for modifying a nominal cell of an integrated digital circuit, the nominal cell containing one or more transistors, the method comprising the steps of:
- (a) selecting a trial set of one or more transistors in the nominal cell, each selected transistor having a nominal gate-length;
- (b) determining trial small bias lengths for the selected trial set of transistors, the trial small bias lengths all less than a predefined fraction of the nominal gate-length;
- (c) adjusting the gate-lengths of the selected trial set of transistors by the small bias lengths to create a trial biased cell;
- (d) comparing the trial biased cell to a current best biased cell with respect to a predefined goal including a tradeoff between reducing a leakage power for the biased cell and reducing an impact on timing delays for the digital circuit;
- and
- (e) updating the current best biased cell based on the comparison.
3 more elements
Dependencies are inferred from the claim text.