G06F 30/373
Design optimisation
G06F30/373 (Design optimisation) appears on 352 US grants and 360 published applications in this corpus.
Search patents in G06F- Granted patents
- 352
- Published applications
- 360
- Assignees
- 189
- Inventors
- 1,001
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 2 |
| 2004 | 2 | 3 |
| 2005 | 3 | 2 |
| 2006 | 2 | 1 |
| 2007 | 0 | 2 |
| 2008 | 2 | 2 |
| 2009 | 0 | 3 |
| 2010 | 3 | 4 |
| 2011 | 2 | 0 |
| 2012 | 5 | 3 |
| 2013 | 5 | 16 |
| 2014 | 16 | 12 |
| 2015 | 15 | 11 |
| 2016 | 11 | 13 |
| 2017 | 16 | 18 |
| 2018 | 15 | 13 |
| 2019 | 16 | 12 |
| 2020 | 31 | 30 |
| 2021 | 37 | 45 |
| 2022 | 33 | 38 |
| 2023 | 38 | 47 |
| 2024 | 32 | 41 |
| 2025 | 38 | 31 |
| 2026 | 28 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Chip design method using secondary development capability of EDA software15 Sep 2026US 12,737,517 B2Batelab Co., Ltd.
- Automated multi-stage design flow based on final quality of result15 Sep 2026US 12,737,523 B2Synopsys, Inc.
- Designing approximate adder circuits using reinforcement learning1 Sep 2026US 12,724,947 B1Auradine, Inc.
- Superconducting impedance matched parametric amplifier11 Aug 2026US 12,704,534 B2Tencent Technology (Shenzhen) Company Limited
- Multiscale thermal reduced order model for transient IC analysis28 Jul 2026US 12,694,183 B1Ansys, Inc.
- Integrated routing assembly and system using same17 Sep 2026US 2026/0278238 A1Molex Incorporated
- Method for alleviating leakage degradation effect in gan device3 Sep 2026US 2026/0262262 A1Beijing Satellite Factory Co., Ltd.
- Systems and Methods for Integrated Circuits (IC) Design using Quantum Evolution Algorithms (QEAs) in Connection with Computer Aided Design (CAD) Software13 Aug 2026US 2026/0236658 A1Ho Chi Minh City University of Technology
- Circuit configuration device and method23 Jul 2026US 2026/0212101 A1ASUSTeK COMPUTER INC.
- Context-aware circuit design for wearable biosymbiotic devices25 Jun 2026US 2026/0180157 A1Arizona Board of Regents on Behalf of the University of Arizona
Most cited
By later US patents
- Gate-length biasing for digital circuit optimization245US 7,441,211 B1Blaze Dfm, Inc. · 2008
- Methods for gate-length biasing using annotation data111US 8,185,865 B2Tela Innovations, Inc. · 2012
- Element removal design in microwave filters55US 8,751,993 B1Resonant Inc. · 2014
- Breakdown voltage multiplying integration scheme26US 9,064,722 B2International Business Machines Corporation · 2015
- Decoupling capacitor insertion using hypergraph connectivity analysis23US 8,479,136 B2International Business Machines Corporation · 2013