Breakdown voltage multiplying integration scheme

A circuit comprising:

• a first field effect transistor having a gate, a drain terminal, and a source terminal, said first field effect transistor comprising one of an n-channel transistor and a p-channel transistor;
• and
• a second field effect transistor having a gate, a drain terminal, and a source terminal, said second field effect transistor also comprising said one of an n-channel transistor and a p-channel transistor;
• wherein:
• said source terminal of said first field effect transistor is coupled to said drain terminal of said second field effect transistor;
• and
• said gate of said second field effect transistor is coupled to said drain terminal of said second field effect transistor;
• wherein:
• said drain terminal of said first field effect transistor comprises an overall drain interconnected with external circuitry;
• said gate of said first field effect transistor comprises an overall gate interconnected with said external circuitry;
• said source terminal of said second field effect transistor comprises an overall source interconnected with said external circuitry;
• and
• said source terminal of said first field effect transistor, said drain terminal of said second field effect transistor, and said gate of said second field effect transistor are not interconnected with said external circuitry.