Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process

A computer system comprising:

• a non-transitory computer readable storage medium encoded with a computer program code;
• and
• a processor coupled to the computer readable storage medium, the processor being configured to execute the computer program code, the computer program code being arranged to cause the processor to:
• receive a layout design of a conductive feature, the conductive feature being a portion of an integrated circuit to be manufactured by a predefined fabrication process;
• determine if a geometry configuration of the layout design of the conductive feature is within a first set of predetermined criteria or a second set of predetermined criteria different from the first set of predetermined criteria;
• generate a bias-adjusted layout design of the conductive feature according to a first layout bias rule after determining that the geometry configuration of the layout design of the conductive feature falls within the first set of predetermined criteria, wherein at least one of the first set of predetermined criteria or the second set of predetermined criteria comprises a threshold ratio or a feature width of a layout design of a neighboring conductive feature;
• and
• generate the bias-adjusted layout design of the conductive feature according to a second layout bias rule different from the first layout bias rule after determining that the geometry configuration of the layout design of the conductive feature falls within the second set of predetermined criteria.

A method of generating a bias-adjusted layout design of a conductive feature, the conductive feature being a portion of an integrated circuit, the method comprising:

• receiving a layout design of the conductive feature;
• dividing the layout design into one or more polygons;
• applying, by a hardware processor, bias adjustments to contours of the one or more polygons, wherein:
• each bias adjustment of the bias adjustments for a polygon of the one or more polygons is based on dimensions of one or more features, each feature of the one or more features belonging to a same mask as the polygon, and
• at least one bias adjustment of the bias adjustments for the polygon of the one or more polygons is based on a threshold ratio or a width of a neighboring feature of the one or more features belonging to the same mask;
• and
• generating the bias-adjusted layout design of the conductive feature according to the bias adjustments applied to the contours of the polygons.