Multi-chip semiconductor arrangements using flip chip dies
AssigneeLSI Logic Corporation
InventorMichael D. Rostoker
Life of this patent
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Abstract
Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.
Claims8
A double-sided semiconductor die, comprising:
- a single-layer semiconductor die having a first surface and a second surface opposite the first surface;
- circuit elements formed within the first surface;
- a first plurality of raised bump contacts disposed on the first surface, and connected to the circuit elements;
- a second plurality of raised bump contacts disposed on the a second surface, at least a one portion of the second plurality of raised bump contacts connected through the die to the circuit elements on the first surface of the die;
- and
- conductive vias connecting at least one of the first plurality of raised bump contacts to at least one of the second plurality of raised bump contacts, said conductive vias consisting of conductive cores surrounded by insulation and disposed through holes formed in the die from the first surface to the second surface.
A flip-chip die assembly with increased bond pad density within a given footprint area, comprising:
- a first semiconductor die having a first surface, a peripheral area of the first surface, and a second surface opposite the first surface;
- first bond pads disposed in the peripheral area of the first surface;
- at least one second semiconductor die having a top surface, a bottom surface, and a peripheral area of the top surface, said at least one second semiconductor die being smaller than said first semiconductor die and mounted by its bottom surface to the first surface of the first semiconductor die, whereby the first bond pads remain exposed;
- and
- second bond pads disposed on the top surface of the at least one second semiconductor die along the peripheral area thereof,
- wherein the first and second bond pads provide for making external connections to the first and at least one second semiconductor dies, respectively.
Dependencies are inferred from the claim text.