G06F 30/396
Clock trees
G06F30/396 (Clock trees) appears on 730 US grants and 606 published applications in this corpus.
Search patents in G06F- Granted patents
- 730
- Published applications
- 606
- Assignees
- 176
- Inventors
- 1,432
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1995 | 1 | 0 |
| 1996 | 3 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 3 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 0 |
| 2002 | 0 | 1 |
| 2003 | 1 | 4 |
| 2004 | 3 | 8 |
| 2005 | 5 | 12 |
| 2006 | 17 | 17 |
| 2007 | 14 | 21 |
| 2008 | 22 | 30 |
| 2009 | 23 | 22 |
| 2010 | 22 | 19 |
| 2011 | 29 | 18 |
| 2012 | 35 | 30 |
| 2013 | 32 | 26 |
| 2014 | 54 | 38 |
| 2015 | 38 | 46 |
| 2016 | 38 | 31 |
| 2017 | 44 | 35 |
| 2018 | 39 | 36 |
| 2019 | 56 | 28 |
| 2020 | 47 | 18 |
| 2021 | 49 | 30 |
| 2022 | 27 | 27 |
| 2023 | 34 | 48 |
| 2024 | 29 | 23 |
| 2025 | 40 | 20 |
| 2026 | 19 | 18 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Balancing buffer insertion for clock H-trees22 Sep 2026US 12,743,573 B1Cadence Design Systems, Inc.
- Automated multi-stage design flow based on final quality of result15 Sep 2026US 12,737,523 B2Synopsys, Inc.
- Method for determining performance of sequential logic elements and device8 Sep 2026US 12,730,952 B2Changxin Memory Technologies, Inc.
- Route-based cell merging8 Sep 2026US 12,730,957 B1Cadence Design Systems, Inc.
- Non-critical child node-based insertion delay optimization in circuit design8 Sep 2026US 12,730,958 B1Cadence Design Systems, Inc.
- Clock signal distribution system, integrated circuit device and method24 Sep 2026US 2026/0288195 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method, apparatus, device, and storage medium for evaluating clock tree20 Aug 2026US 2026/0244239 A1Beijing Youzhuju Network Technology Co., Ltd.
- Integrated Circuit Design with Logic Cells Associated with Dependent Operating Elements Arranged in a Widening Structure30 Jul 2026US 2026/0220345 A1Google Inc.
- Dual-edge pulse modeling in circuit design testing23 Jul 2026US 2026/0212098 A1International Business Machines Corporation
- Memory with bundle-wide access lines, method of reading from the same and method of manufacturing same18 Jun 2026US 2026/0170220 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Presilicon disk model for design, development and validation140US 7,031,902 B1Western Digital Technologies, Inc. · 2006
- Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew71US 5,410,491 AKabushiki Kaisha Toshiba · 1995
- Automatic synthesis of clock distribution networks67US 8,205,182 B1Cadence Design Systems, Inc. · 2012
- Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations63US 5,526,278 AAT&T Corp. · 1996
- Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew60US 5,557,779 AKabushiki Kaisha Toshiba · 1996