US 5,557,779 A · Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew

Abstract

A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

Claims15

Dependent claims

A method for distributing a control signal in a wiring-pattern network formed on a semiconductor substrate where said control signal is supplied from a root driver cell via repeating buffer cells to a plurality of terminal cells, the method comprising the steps of:

grouping said plurality of terminal cells into a plurality of clusters containing at least one of said terminal cells;
forming a binary-tree-shaped wiring pattern path where said root driver cell is constituted as a root node and said clusters are constituted as leaf nodes;
inserting said repeating buffer cells as branch nodes into portions of the binary-tree-shaped wiring pattern path at which each of delay times of said control signal propagating therein is minimized and dividing the binary-tree-shaped wiring pattern path into multi-stage hierarchical sub-trees;
calculating delay times of said control signal propagating from each of said branch nodes to each of said leaf nodes, said calculating step being successively repeated from the lowermost ones of said branch nodes to the uppermost one of said branch nodes;
setting physical positions of said branch nodes on the semiconductor substrate where a difference among said delay times becomes minimum;
updating previous entire information about a circuit connection when said repeating buffer cells are inserted;
separating said repeating buffer cells from other cells being overlapped with said repeating buffer cells on said binary-tree-shaped wiring pattern path;
correcting arrangement information about positions of all the cells on the semiconductor substrate so as not to have any of the cells being overlapped;
and
determining a final wiring-pattern path among each of said branch nodes.

7 more elements

Dependencies are inferred from the claim text.

Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew

Life of this patent

Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew

Life of this patent

Abstract

Claims15