Method for determining performance of sequential logic elements and device

An electronic device, comprising at least one processor and a memory, wherein

• the memory stores computer-executable instructions;
• and
• the at least one processor executes the computer-executable instructions stored in the memory to perform operations comprising:
• obtaining a performance check file corresponding to each of sequential logic elements of a circuit;
• separately simulating the circuit based on the performance check file corresponding to each of the sequential logic elements to obtain a simulation result, by using a plurality of different simulation waveforms, wherein the plurality of different simulation waveforms comprise different clock signals and different input data signals, wherein the performance check file is used to check, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and wherein identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result;
• determining a smallest target characteristic parameter corresponding to target sequential logic elements on a same path in the simulation result and a target simulation waveform corresponding to the smallest target characteristic parameter;
• determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path;
• and
• adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path.

A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the computer-executable instructions cause the processor to perform operations comprising:

• obtaining a performance check file corresponding to each of sequential logic elements of a circuit;
• separately simulating the circuit based on the performance check file corresponding to each of the sequential logic elements to obtain a simulation result, by using a plurality of different simulation waveforms, wherein the plurality of different simulation waveforms comprise different clock signals and different input data signals, wherein the performance check file is used to check, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and wherein identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result;
• determining a smallest target characteristic parameter corresponding to target sequential logic elements on a same path in the simulation result and a target simulation waveform corresponding to the smallest target characteristic parameter;
• determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path;
• and
• adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path.