Automatic synthesis of clock distribution networks
AssigneeCadence Design Systems, Inc.
InventorsRadu Zlatanovici, Christoph Albrecht, Saurabh Kumar Tiwary
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Abstract
In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.
Claims25
A method for designing an integrated circuit, the method comprising using a processor to perform one or more of the following:
- automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions for each clock source;
- automatically synthesizing an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions;
- and
- automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.
A machine-readable product comprising:
- a non-transitory machine readable medium having machine readable program code stored therein that is executable by a machine to design an integrated circuit including
- machine readable program code to automatically partition clock sinks of an integrated circuit design into a plurality of partitions;
- machine readable program code to automatically synthesize an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions;
- and
- machine readable program code to automatically synthesize clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.
A system to design an integrated circuit, the system comprising:
- a processor;
- a processor readable medium coupled to the processor, the processor readable medium to store instructions that when executed by the processor cause the processor to perform operations to automatically synthesize a clock distribution network for an integrated circuit design, the operations including
- partitioning clock sinks of an integrated circuit design into a plurality of partitions;
- synthesizing an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions;
- and
- synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.
Dependencies are inferred from the claim text.