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US 12,730,958 B1Granted
Non-critical child node-based insertion delay optimization in circuit design
AssigneeCadence Design Systems, Inc.
InventorsNecati Uysal, Sheiny Fabre Almeida, Natarajan Viswanathan, Charles Jay Alpert, Amin Farshidi
Life of this patent
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Abstract
Various embodiments provide for optimizing (e.g., reducing) insertion delay in a circuit design based on one or more non-critical child nodes of a critical node of a routing tree, which can be performed by an electronic design automation (EDA) software to optimize (e.g., reduce) insertion delay in a clock tree of a circuit design.
Claims20
A system comprising:
- a memory storing instructions;
- and
- a hardware processor communicatively coupled to the memory and configured by the instructions to perform operations comprising:
- accessing circuit design data that describes a circuit design comprising a clock tree, the clock tree comprising one or more clock nodes of the circuit design;
- determining a critical path of the clock tree that has a longest insertion delay in the clock tree, the critical path passing through a critical clock node of the clock tree, the critical path being between a parent clock node of the critical clock node and a critical child clock node of the critical clock node;
- determining a set of non-critical child clock nodes of the critical clock node;
- determining, based on the set of non-critical child clock nodes, a possible transformation to be applied to the clock tree, the possible transformation being configured to reduce a load driven of the critical clock node, the possible transformation comprising at least one of:
- one or more non-critical child clock node movements that move one or more non-critical child clock nodes of the set of non-critical child clock nodes closer to the critical clock node;
- or
- one or more non-critical child node size adjustments that downsize one or more non-critical child clock nodes of the set of non-critical child clock nodes;
- determining, based on an outcome of the determining of the possible transformation, whether to apply the possible transformation to the clock tree;
- and
- in response to determining that the possible transformation is to be applied to the clock tree, modifying the circuit design to apply the possible transformation to the clock tree.
10 more elements
A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
- accessing circuit design data that describes a circuit design comprising a clock tree, the clock tree comprising one or more clock nodes of the circuit design;
- determining a set of non-critical child clock nodes of a critical clock node, the critical clock node being on a critical path of the clock tree, the critical path being between a parent clock node of the critical clock node and a critical child clock node of the critical clock node, the critical path having a longest insertion delay in the clock tree;
- determining, based on the set of non-critical child clock nodes, a possible transformation to be applied to the clock tree, the possible transformation being configured to reduce a load driven of the critical clock node, the possible transformation comprising at least one of:
- one or more non-critical child node movements that move one or more non-critical child clock nodes of the set of non-critical child clock nodes closer to the critical clock node;
- or
- one or more non-critical child node size adjustments that downsize one or more non-critical child clock nodes of the set of non-critical child clock nodes;
- determining, based on an outcome of the determining of the possible transformation, whether to apply the possible transformation to the clock tree;
- and
- in response to determining that the possible transformation is to be applied to the clock tree, modifying the circuit design to apply the possible transformation to the clock tree.
6 more elements
A method comprising:
- accessing, by a hardware processor, circuit design data that describes a circuit design comprising a routing tree, the routing tree comprising one or more nodes of the circuit design,
- determining, by the hardware processor, a set of non-critical child nodes of a critical node, the critical node being on a critical path of the routing tree, the critical path being between a parent node of the critical node and a critical child node of the critical node, the critical path having a longest insertion delay in the routing tree;
- determining, by the hardware processor, a possible transformation to the routing tree based on the set of non-critical child nodes, the possible transformation being configured to reduce a load driven by the critical node, the possible transformation comprising at least one of:
- one or more non-critical child node movements that move one or more non-critical child nodes of the set of non-critical child nodes closer to the critical node;
- or
- one or more non-critical child node size adjustments that downsize one or more non-critical child nodes of the set of non-critical child nodes;
- determining, by the hardware processor and based on an outcome of the determining of the possible transformation, whether to apply the possible transformation to the routing tree;
- and
- in response to determining that the possible transformation is to be applied to the routing tree, modifying, by the hardware processor, the circuit design to apply the possible transformation to the routing tree.
6 more elements
Dependencies are inferred from the claim text.