Dual-edge pulse modeling in circuit design testing

A computer system including:

• at least one computing device;
• a set of one or more computer readable storage media;
• and
• program instructions, collectively stored in the set of one or more computer readable storage media, for causing the at least one computing device to perform computer operations including:
• identifying, from an input specification of a circuit, a dual-edge pulse clock that is based on a source clock specified in the input specification, the dual-edge pulse clock including leading-edge pulses triggered based on leading edges of the source clock and trailing-edge pulses triggered based on trailing edges of the source clock;
• and
• modeling the dual-edge pulse clock by a set of clock signals for a timing analysis of the circuit, the set of clock signals including one clock signal that models the leading-edge pulses of the dual-edge pulse clock and another clock signal that models the trailing-edge pulses of the dual-edge pulse clock.

A computer program product including:

• a set of one or more computer readable storage media;
• and
• program instructions, collectively stored in the set of one or more computer readable storage media, for causing at least one computing device to perform computer operations including:
• identifying, from an input specification of a circuit, a dual-edge pulse clock that is based on a source clock specified in the input specification, the dual-edge pulse clock including leading-edge pulses triggered based on leading edges of the source clock and trailing-edge pulses triggered based on trailing edges of the source clock;
• and
• modeling the dual-edge pulse clock by a set of clock signals for a timing analysis of the circuit, the set of clock signals including one clock signal that models the leading-edge pulses of the dual-edge pulse clock and another clock signal that models the trailing-edge pulses of the dual-edge pulse clock.

A computer-implemented method including:

• identifying, from an input specification of a circuit, a plurality of dual-edge pulse clocks based on a source clock specified in the input specification, each dual-edge pulse clock of the identified plurality of dual-edge pulse clocks including respective leading-edge pulses triggered based on leading edges of the source clock and trailing-edge pulses triggered based on trailing edges of the source clock, wherein the identified plurality of dual-edge pulse clocks are of a setup test, of a timing analysis of the circuit, for testing mid-cycle edge uncertainty of the source clock in a multi-cycle path in which data provided from a latch of the circuit is to be flushed through one or more sequentially-next latches of the circuit and arrive at another latch of the circuit, the testing being based on an earliest mid-cycle edge arrival time of the source clock and a latest mid-cycle edge arrival time of the source clock;
• modeling each dual-edge pulse clock of the identified plurality of dual-edge pulse clocks, wherein the modeling models:
• (i) a first dual-edge pulse clock of the identified plurality of dual-edge pulse clocks based on an early-arrival source clock, representing the earliest mid-cycle edge arrival time, using a respective set of clock signals, as early-arrival clock signals, that includes:
• a first clock signal that models pulses, of the first dual-edge pulse clock, triggered based on leading edges of the early-arrival source clock;
• and
• a second clock signal that models pulses, of the first dual-edge pulse clock, triggered based on trailing edges of the early-arrival source clock, the trailing edges of the early-arrival source clock being mid-cycle edges of the early-arrival source clock;
• and
• (ii) a second dual-edge pulse clock of the identified plurality of dual-edge pulse clocks based on a late-arrival source clock, representing the latest mid-cycle edge arrival time, using a respective set of clock signals, as late-arrival clock signals, that includes:
• a first clock signal that models pulses, of the second dual-edge pulse clock, triggered based on leading edges of the late-arrival source clock;
• and
• a second clock signal that models pulses, of the second dual-edge pulse clock, triggered based on trailing edges of the late-arrival source clock, the trailing edges of the late-arrival source clock being mid-cycle edges of the late-arrival source clock;
• and
• performing the timing analysis based on the modeling, wherein the timing analysis includes the setup test for testing mid-cycle edge uncertainty and pulse width testing, the pulse width testing determining pulse width of the respective leading-edge pulses of a selected dual-edge pulse clock, of the identified plurality of dual-edge pulse clocks, as a width of pulses of one clock signal that models the respective leading-edge pulses of the selected dual-edge pulse clock, and determining pulse width of the respective trailing-edge pulses of the selected dual-edge pulse clock as a width of pulses of another clock signal that models the respective trailing-edge pulses of the selected dual-edge pulse clock.

A computer system including:

• at least one computing device;
• a set of one or more computer readable storage media;
• and
• program instructions, collectively stored in the set of one or more computer readable storage media, for causing the at least one computing device to perform computer operations including:
• identifying, from an input specification of a circuit, a plurality of dual-edge pulse clocks based on a source clock specified in the input specification, each dual-edge pulse clock of the identified plurality of dual-edge pulse clocks including respective leading-edge pulses triggered based on leading edges of the source clock and trailing-edge pulses triggered based on trailing edges of the source clock, wherein the identified plurality of dual-edge pulse clocks are of a setup test, of a timing analysis of the circuit, for testing mid-cycle edge uncertainty of the source clock in a multi-cycle path in which data provided from a latch of the circuit is to be flushed through one or more sequentially-next latches of the circuit and arrive at another latch of the circuit, the testing being based on an earliest mid-cycle edge arrival time of the source clock and a latest mid-cycle edge arrival time of the source clock;
• modeling each dual-edge pulse clock of the identified plurality of dual-edge pulse clocks, wherein the modeling models:
• (i) a first dual-edge pulse clock of the identified plurality of dual-edge pulse clocks based on an early-arrival source clock, representing the earliest mid-cycle edge arrival time, using a respective set of clock signals, as early-arrival clock signals, that includes:
• a first clock signal that models pulses, of the first dual-edge pulse clock, triggered based on leading edges of the early-arrival source clock;
• and
• a second clock signal that models pulses, of the first dual-edge pulse clock, triggered based on trailing edges of the early-arrival source clock, the trailing edges of the early-arrival source clock being mid-cycle edges of the early-arrival source clock;
• and
• (ii) a second dual-edge pulse clock of the identified plurality of dual-edge pulse clocks based on a late-arrival source clock, representing the latest mid-cycle edge arrival time, using a respective set of clock signals, as late-arrival clock signals, that includes:
• a first clock signal that models pulses, of the second dual-edge pulse clock, triggered based on leading edges of the late-arrival source clock;
• and
• a second clock signal that models pulses, of the second dual-edge pulse clock, triggered based on trailing edges of the late-arrival source clock, the trailing edges of the late-arrival source clock being mid-cycle edges of the late-arrival source clock;
• and
• performing the timing analysis based on the modeling, wherein the timing analysis includes the setup test for testing mid-cycle edge uncertainty and pulse width testing, the pulse width testing determining pulse width of the respective leading-edge pulses of a selected dual-edge pulse clock, of the identified plurality of dual-edge pulse clocks, as a width of pulses of one clock signal that models the respective leading-edge pulses of the selected dual-edge pulse clock, and determining pulse width of the respective trailing-edge pulses of the selected dual-edge pulse clock as a width of pulses of another clock signal that models the respective trailing-edge pulses of the selected dual-edge pulse clock.