Memory with bundle-wide access lines, method of reading from the same and method of manufacturing same

A method of manufacturing a memory, the method comprising:

• forming structures that comprise components, the components including memory cells, local access managers and a global access manager, the forming structures that comprise components including:
• arranging first ones of the components that comprise the memory cells into first, second, third and fourth banks that are stacked on each other relative to a first direction including, for each of the first to fourth banks, arranging alpha ones and beta ones of the first components into corresponding first and second partitions;
• arranging (A) the first and second banks and (B) the third and fourth banks as corresponding first and second bundles;
• and
• arranging second ones of the components that comprise the local access managers so that, for each of the first, second, third and fourth banks, the first and second partitions are separated from each other by a corresponding one of the local access managers relative to the first direction;
• arranging third ones of the components that comprise the global access manager so that the global access manager separates the first and second bundles relative to the first direction;
• and
• forming intercouplings amongst the components resulting in at least:
• first and second bundle-wide write lines or first and second bundle-wide read lines that separately couple the global access manager correspondingly to the first and second bundles.

A method of reading from a memory, the method comprising:

• accessing first and second bundles of the memory on a mutually exclusive basis;
• the first and second bundles correspondingly being comprised of (A) first and second banks of the memory and (B) third and fourth banks of the memory;
• the first, second, third and fourth banks being stacked on each other relative to a first direction and correspondingly being comprised of memory cells, and each of which including first and second partitions and a local access manager, the memory including a global access manager separating the first and second bundles relative to the first direction, and the global access manager being separately coupled to the first and second bundles by corresponding first and second bundle-wide write lines, and the global access manager including a first delay line and a multiplexer coupled to the first and second bundles by corresponding first and second bundle-wide read lines;
• for a selected one of the memory cells in the corresponding one of first and second bundles, the accessing first and second bundles including:
• providing bank-level signals to the corresponding local access manager thereby causing data to be transferred from the selected one of the memory cells onto the corresponding one of the first and second bundle-wide read lines;
• and
• delaying a control signal by a first delay factor;
• and
• the control signal being configured to cause the multiplexer to select the first or second bundle-wide read line.