G06F 30/398
Design verification or optimisation
Official title: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
G06F30/398 (Design verification or optimisation) appears on 6,135 US grants and 6,223 published applications in this corpus.
Search patents in G06F- Granted patents
- 6,135
- Published applications
- 6,223
- Assignees
- 896
- Inventors
- 10,273
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 4 | 0 |
| 1993 | 7 | 0 |
| 1994 | 8 | 0 |
| 1995 | 17 | 0 |
| 1996 | 17 | 0 |
| 1997 | 18 | 0 |
| 1998 | 12 | 0 |
| 1999 | 16 | 0 |
| 2000 | 20 | 0 |
| 2001 | 21 | 5 |
| 2002 | 27 | 29 |
| 2003 | 38 | 45 |
| 2004 | 46 | 72 |
| 2005 | 53 | 87 |
| 2006 | 70 | 95 |
| 2007 | 68 | 97 |
| 2008 | 73 | 130 |
| 2009 | 77 | 141 |
| 2010 | 107 | 152 |
| 2011 | 118 | 111 |
| 2012 | 156 | 169 |
| 2013 | 287 | 280 |
| 2014 | 427 | 427 |
| 2015 | 368 | 431 |
| 2016 | 393 | 451 |
| 2017 | 453 | 393 |
| 2018 | 375 | 331 |
| 2019 | 524 | 329 |
| 2020 | 522 | 377 |
| 2021 | 402 | 345 |
| 2022 | 257 | 349 |
| 2023 | 362 | 458 |
| 2024 | 289 | 315 |
| 2025 | 324 | 315 |
| 2026 | 169 | 289 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Mask optimization for layer accounting for overlap with other layers6 Oct 2026US 12,754,471 B2D2S, Inc.
- Mask optimization for layer based on comparison of components in layer to components in other layers6 Oct 2026US 12,754,472 B2D2S, Inc.
- Mask optimization preferentially accounting for overlap regions6 Oct 2026US 12,754,473 B2D2S, Inc.
- Concurrent mask optimization for multiple layers6 Oct 2026US 12,754,474 B2D2S, Inc.
- Machine learning based metrology for semiconductor specimens6 Oct 2026US 12,754,484 B2Applied Materials Israel Ltd.
- Method of and device for generating layout diagram8 Oct 2026US 2026/0310062 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Kernel function generation method, optical proximity correction method using the kernel function, and mask manufacturing method including the optical proximity correction method8 Oct 2026US 2026/0310064 A1Samsung Electronics Co., Ltd.
- Mask optimization accounting for more critical and less critical overlap regions8 Oct 2026US 2026/0310067 A1D2S, Inc.
- Interactively presenting for minimum overlap shapes in an ic design8 Oct 2026US 2026/0310865 A1D2S, Inc.
- Dummy fill layout optimization method and system8 Oct 2026US 2026/0310873 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- System and methods for converting planar design to FinFET design1,326US 8,816,444 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Method for integrated circuit mask patterning449US 9,256,709 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Parasitic capacitance extraction for FinFETs436US 8,826,213 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process418US 8,887,106 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Design rule checking system and method400US 6,470,489 B1Numerical Technologies, Inc. · 2002