H10W 72/9232
With additional elements interposed between layers
Official title: {with additional elements interposed between layers}
H10W72/9232 (With additional elements interposed between layers) appears on 884 US grants and 960 published applications in this corpus.
Search patents in H10W- Granted patents
- 884
- Published applications
- 960
- Assignees
- 232
- Inventors
- 1,652
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 4 | 0 |
| 1995 | 3 | 0 |
| 1996 | 3 | 0 |
| 1997 | 3 | 0 |
| 1998 | 5 | 0 |
| 1999 | 9 | 0 |
| 2000 | 14 | 0 |
| 2001 | 26 | 15 |
| 2002 | 22 | 35 |
| 2003 | 27 | 35 |
| 2004 | 38 | 27 |
| 2005 | 26 | 56 |
| 2006 | 27 | 41 |
| 2007 | 34 | 56 |
| 2008 | 31 | 74 |
| 2009 | 29 | 51 |
| 2010 | 59 | 55 |
| 2011 | 59 | 43 |
| 2012 | 42 | 33 |
| 2013 | 40 | 50 |
| 2014 | 41 | 29 |
| 2015 | 38 | 43 |
| 2016 | 26 | 34 |
| 2017 | 42 | 39 |
| 2018 | 26 | 30 |
| 2019 | 33 | 33 |
| 2020 | 37 | 46 |
| 2021 | 33 | 32 |
| 2022 | 29 | 35 |
| 2023 | 29 | 19 |
| 2024 | 26 | 26 |
| 2025 | 18 | 15 |
| 2026 | 3 | 8 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Etch profile control of interconnect structures4 Aug 2026US 12,701,976 B2Taiwan Semiconductor Manufacturing Company, Ltd.
- Semiconductor device2 Jun 2026US 12,648,488 B2United Microelectronics Corp.
- Expanded head pillar for bump bonds23 Dec 2025US 12,506,097 B2Texas Instruments Incorporated
- Seal ring for hybrid-bond18 Nov 2025US 12,476,206 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for manufacturing semiconductor device, and semiconductor device3 Sep 2026US 2026/0262531 A1Resonac Corporation
- Semiconductor element and semiconductor apparatus2 Jul 2026US 2026/0190985 A1Sony Semiconductor Solutions Corporation
- Semiconductor package including an electrode25 Jun 2026US 2026/0182438 A1SK hynix Inc.
- Semiconductor chip and semiconductor package21 May 2026US 2026/0144169 A1Samsung Electronics Co., Ltd.
- Electronic device including an outermost layer having oxide material, assembly structure and method of manufacturing the same30 Apr 2026US 2026/0123499 A1Nanya Technology Corporation
Most cited
By later US patents
- Method and apparatus for 3D interconnect542US 8,076,237 B2ASM America, Inc. · 2011
- Strain-compensating fill patterns for controlling semiconductor chip package interactions241US 8,441,131 B2Globalfoundries Inc. · 2013
- Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure234US 9,723,716 B2Infineon Technologies AG · 2017
- Integrated circuit bonding pads including closed vias and closed conductive patterns159US 6,222,270 B1Samsung Electronics Co., Ltd. · 2001
- Microcap wafer-level package with vias151US 6,228,675 B1Agilent Technologies, Inc. · 2001