US 8,441,131 B2 · Strain-compensating fill patterns for controlling semiconductor chip package interactions

Abstract

Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.

Claims25

Dependent claims

A semiconductor chip, comprising:

a bond pad;
a metallization layer below said bond pad, wherein said metallization layer comprises a bond pad area below said bond pad and a field area surrounding said bond pad area;
and
a plurality of conductive device features in said metallization layer, said plurality of conductive device features comprising a first group of conductive device features in said bond pad area and a second group of conductive device features in said field area, wherein said first group has a first feature distribution density and said second group has a second feature distribution density that is less than said first feature distribution density, at least a portion of said plurality of conductive device features are dummy device features that do not transmit electrical current during electrical operation of said semiconductor chip, and at least one of said dummy device features is a metal plug that is not electrically connected to any other dummy device features of said semiconductor chip.

1 more element

A semiconductor chip, comprising:

a metallization system comprising a plurality of metallization layers, at least one of said plurality of metallization layers comprising one of a low-k dielectric material and an ultra-low-k dielectric material;
a bond pad in a last metallization layer of said metallization system;
a first flexible structure positioned in said metallization system, said first flexible structure comprising a first upper end and a first lower end, wherein said first upper end is below said bond pad, said first lower end is in a metallization layer of said metallization system below said first upper end, and said first upper end is closer to a centerline of said semiconductor chip than said first lower end, said centerline passing through an approximate geometric center of said semiconductor chip;
and
a second flexible structure positioned in said metallization system, said second flexible structure comprising a second upper end and a second lower end, wherein said second upper end is below said bond pad, said second lower end is in a metallization layer of said metallization system below said second upper end, said second upper end is closer to said centerline than said second lower end, and said first upper is closer to said centerline than said second upper end, at least one of said first and second flexible structures contacting said at least one of said plurality of metallization layers comprising at least one of a low-k dielectric material and an ultra-low-k dielectric material.

2 more elements

Dependencies are inferred from the claim text.

Strain-compensating fill patterns for controlling semiconductor chip package interactions

Life of this patent

Strain-compensating fill patterns for controlling semiconductor chip package interactions

Life of this patent

Abstract

Claims25