Semiconductor element and semiconductor apparatus
AssigneeSony Semiconductor Solutions Corporation
InventorsKazuyuki TOMIDA, Shinichi MIYAKE, Katsuhiko HANZAWA
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Abstract
A manufacturing process is simplified. A semiconductor element includes: a first wiring region of a first semiconductor substrate; a second wiring region of a second semiconductor substrate; a first pad embedded in a surface of the first wiring region; a second pad embedded in a surface of the second wiring region and at a position overlapping the first pad when the first wiring region and the second wiring region are bonded; a capacitive element disposed on any one of the first pad and the second pad; and a capacitive element connection pad embedded in the first wiring region and connected to the second pad when the first wiring region and the second wiring region are bonded.
Claims6
A semiconductor element, comprising:
- a first semiconductor substrate;
- a second semiconductor substrate;
- a first wiring region disposed adjacent to the first semiconductor substrate;
- a second wiring region disposed adjacent to the second semiconductor substrate and having a surface bonded to a surface of the first wiring region;
- a first pad embedded in the surface of the first wiring region;
- a second pad embedded in the surface of the second wiring region and disposed at a position overlapping the first pad in plan view when the surface of the first wiring region and the surface of the second wiring region are bonded;
- a capacitive element configured by sequentially stacking a first electrode, a dielectric layer, and a second electrode disposed on any one of the first pad and the second pad;
- and
- a capacitive element connection pad that is a pad embedded in the surface of the first wiring region and connected to the second pad when the surface of the first wiring region and the surface of the second wiring region are bonded.
A semiconductor apparatus, comprising:
- a first semiconductor substrate;
- a second semiconductor substrate;
- a first wiring region disposed adjacent to the first semiconductor substrate;
- a second wiring region disposed adjacent to the second semiconductor substrate and having a surface bonded to a surface of the first wiring region;
- a first pad embedded in the surface of the first wiring region;
- a second pad embedded in the surface of the second wiring region and disposed at a position overlapping the first pad in plan view when the surface of the first wiring region and the surface of the second wiring region are bonded;
- a capacitive element configured by sequentially stacking a first electrode, a dielectric layer, and a second electrode disposed on any one of the first pad and the second pad;
- a capacitive element connection pad that is a pad embedded in the surface of the first wiring region and connected to the second pad when the surface of the first wiring region and the surface of the second wiring region are bonded;
- a first electronic circuit connected to the first pad via a wiring disposed in the first wiring region;
- and
- a second electronic circuit connected to the capacitive element connection pad via a wiring disposed in the first wiring region.
Dependencies are inferred from the claim text.