H10W 70/655
Fan-out layouts
H10W70/655 (Fan-out layouts) appears on 3,904 US grants and 4,086 published applications in this corpus.
Search patents in H10W- Granted patents
- 3,904
- Published applications
- 4,086
- Assignees
- 647
- Inventors
- 5,543
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 3 | 0 |
| 1978 | 4 | 0 |
| 1979 | 1 | 0 |
| 1980 | 5 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 1 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 3 | 0 |
| 1988 | 7 | 0 |
| 1989 | 7 | 0 |
| 1990 | 5 | 0 |
| 1991 | 17 | 0 |
| 1992 | 13 | 0 |
| 1993 | 15 | 0 |
| 1994 | 26 | 0 |
| 1995 | 21 | 0 |
| 1996 | 22 | 0 |
| 1997 | 40 | 0 |
| 1998 | 46 | 0 |
| 1999 | 67 | 0 |
| 2000 | 69 | 0 |
| 2001 | 75 | 41 |
| 2002 | 100 | 99 |
| 2003 | 97 | 136 |
| 2004 | 112 | 146 |
| 2005 | 135 | 177 |
| 2006 | 81 | 125 |
| 2007 | 112 | 175 |
| 2008 | 122 | 173 |
| 2009 | 103 | 144 |
| 2010 | 117 | 134 |
| 2011 | 142 | 154 |
| 2012 | 122 | 128 |
| 2013 | 144 | 121 |
| 2014 | 128 | 142 |
| 2015 | 139 | 156 |
| 2016 | 154 | 127 |
| 2017 | 147 | 156 |
| 2018 | 155 | 205 |
| 2019 | 190 | 279 |
| 2020 | 237 | 312 |
| 2021 | 208 | 232 |
| 2022 | 180 | 207 |
| 2023 | 190 | 146 |
| 2024 | 165 | 146 |
| 2025 | 124 | 91 |
| 2026 | 43 | 134 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor package6 Oct 2026US 12,757,763 B2Samsung Electronics Co., Ltd.
- Semiconductor package29 Sep 2026US 12,751,330 B2Samsung Electronics Co., Ltd.
- Integrated circuit packages and methods of forming the same22 Sep 2026US 12,745,645 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Apparatus and method for electroless surface finishing on glass15 Sep 2026US 12,740,460 B2Intel Corporation
- Package structure and manufacturing method thereof8 Sep 2026US 12,733,507 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit packages and methods of forming the same8 Oct 2026US 2026/0314429 A1Taiwan Semiconductor Manufacturing Company.Ltd
- System-in-package (sip) configured to receive multiple memory dies8 Oct 2026US 2026/0314443 A1QUALCOMM Incorporated
- Package structure and manufacturing method thereof1 Oct 2026US 2026/0305362 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor package1 Oct 2026US 2026/0305402 A1Mediatek Inc.
- 3D fan-out packaging structure of interconnection system with ultra-high density and method for manufacturing THE same1 Oct 2026US 2026/0305450 A1SJ Semiconductor(Jiangyin) Corporation
Most cited
By later US patents
- Fan-out interconnect structure and method for forming same1,030US 9,368,460 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Embedded wafer-level bonding approaches616US 8,361,842 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2013
- Three-dimensional multi-chip pad array carrier602US 5,222,014 AMotorola, Inc. · 1993
- Direct build-up layer on an encapsulated die package600US 6,271,469 B1Intel Corporation · 2001