Three-dimensional multi-chip pad array carrier

A stacking semiconductor multiple chip module comprising:

• a lower chip carrier of thermally conductive material having a plurality of solder bumps on both top and bottom surfaces of the carrier;
• a first semiconductor die electrically and physically attached to the lower chip carrier;
• an upper chip carrier substrate of thermally conductive material having a top and a bottom surface;
• a plurality of solder bumps on the bottom surface of the upper chip carrier substrate;
• a second semiconductor die mounted and electrically coupled to the upper chip carrier substrate, wherein the lower chip carrier substrate and the upper chip carrier substrate are electrically connected to each other by solder joints;
• and
• a lid capping the first semiconductor die and serving as a positive stand-off to create hour-glass solder joints between the upper chip carrier substrate and the lower chip carrier substrate.

A method for making a stackable semiconductor multiple chip module comprising the steps of:

• providing a lower chip carrier substrate of thermally conductive material;
• depositing a plurality of solder bumps on both top and bottom surfaces of the lower chip carrier substrate;
• mounting a first semiconductor die onto the lower chip carrier substrate and electrically coupling it to said lower chip carrier substrate;
• placing a lid over the first semiconductor die to serve as a positive stand-off;
• providing an upper chip carrier substrate of thermally conductive material, the upper chip carrier substrate having a top and a bottom surface;
• depositing a plurality of solder bumps on the bottom surface of the upper chip carrier substrate;
• mounting a second semiconductor die to the upper chip carrier substrate and electrically coupling it to the same;
• aligning the upper chip carrier substrate to the lower chip carrier substrate by position of the solder bumps;
• and
• reflowing the solder bumps together to achieve physical and electrical connections.