Semiconductor package

A semiconductor package comprising:

• a first redistribution structure including a top surface;
• a chip arranged on the top surface of the first redistribution structure, the chip having a top surface, bottom surface, and side surfaces;
• and
• a package body arranged on the first redistribution structure to cover the side surfaces of the chip,
• wherein the first redistribution structure comprises:
• a plurality of redistribution layers stacked in a vertical direction;
• a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other;
• a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting redistribution layers of the plurality of redistribution layers to each other;
• a plurality of barrier layers formed between upper surfaces and side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers;
• and
• a plurality of barrier seed layers formed on lower surfaces of the plurality of redistribution layers and side surfaces and lower surfaces of the plurality of redistribution vias and between the plurality of redistribution insulating layers.

A semiconductor package comprising:

• a first redistribution structure having a top surface;
• a chip arranged on the top surface of the first redistribution structure, the chip having a top surface, bottom surface, and side surfaces;
• and
• a package body arranged on the first redistribution structure to cover the side surfaces of the chip,
• wherein the first redistribution structure comprises:
• a plurality of redistribution layers stacked in a vertical direction;
• a plurality of redistribution insulating layers that insulate the plurality of redistribution layers from each other;
• a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other;
• and
• a plurality of barrier layers formed between upper surfaces, side surfaces, and lower surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers, and between side surfaces of the plurality of redistribution vias and the plurality of redistribution insulating layers.