Semiconductor package

A semiconductor package, comprising:

• a substrate;
• a first semiconductor chip on the substrate and including a through via in the first semiconductor chip, the first semiconductor chip having a first width in a first direction;
• a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a second width in the first direction;
• a first molding layer that surrounds the first semiconductor chip in a plan view;
• a second molding layer that surrounds the second semiconductor chip in the plan view;
• and
• a lower redistribution layer below the first semiconductor chip, wherein the lower redistribution layer includes:
• a lower dielectric layer;
• a plurality of lower redistribution patterns in the lower dielectric layer;
• and
• a first lower redistribution pad and a second lower redistribution pad that are electrically connected to the lower redistribution patterns,
• wherein the first lower redistribution pad is coupled to the through via through one of the lower redistribution patterns,
• wherein the second lower redistribution pad is coupled to a conductive post through another of the lower redistribution patterns,
• wherein the second width is greater than the first width, and
• wherein a portion of a top surface of the first molding layer is in contact with an entirety of a bottom surface of the second molding layer.

A semiconductor package, comprising:

• a first redistribution substrate that includes a first dielectric layer, a first seed pattern, and a first conductive pattern on the first seed pattern, wherein the first dielectric layer includes a photo-imageable polymer;
• a solder ball on a bottom surface of the first redistribution substrate;
• a first semiconductor chip on a top surface of the first redistribution substrate and including a plurality of through vias in the first semiconductor chip, wherein the first semiconductor chip includes a plurality of first bonding pads on an upper portion of the first semiconductor chip;
• a conductive post on the top surface of the first redistribution substrate and laterally spaced apart from the first semiconductor chip;
• a second semiconductor chip on a top surface of each of the first semiconductor chip and the conductive post and coupled to the through vias and the conductive post, wherein the second semiconductor chip includes a plurality of second bonding pads on a lower portion of the second semiconductor chip;
• a connection structure on the top surface of the first redistribution substrate and laterally spaced apart from the conductive post, the first semiconductor chip, and the second semiconductor chip;
• a first molding layer on the top surface of the first redistribution substrate, wherein the first molding layer is on sidewalls of the connection structure and surrounds the first semiconductor chip and the second semiconductor chip in a plan view;
• and
• a second redistribution substrate on the first molding layer and the connection structure,
• wherein the second redistribution substrate is coupled to the connection structure,
• wherein the first bonding pads are in contact with the second bonding pads, and
• wherein a width in a first direction of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip, the first direction being parallel to the bottom surface of the first redistribution substrate.