US 12,745,645 B2Granted

Integrated circuit packages and methods of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHsien-Wei Chen, Chieh-Lung Lai, Meng-Liang Lin, Chun-Yueh Yang, Shin-Puu Jeng

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Abstract

An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Claims20

Dependent claims

An integrated circuit package comprising:

an interposer comprising:
a first redistribution layer;
a second redistribution layer over the first redistribution layer in a central region of the interposer;
a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view;
a third redistribution layer over the second redistribution layer and the dielectric layer;
and
a first direct via embedded in the dielectric layer, wherein the first direct via is spaced apart from the second redistribution layer by the dielectric layer, wherein the dielectric layer contacts and extends along sidewalls of the first direct via, wherein a conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via;
and
an integrated circuit die over the third redistribution layer of the interposer, wherein the integrated circuit die is coupled to the conductive feature of the first redistribution layer through the first direct via.

6 more elements

An integrated circuit package comprising:

a package substrate comprising:
a substrate core, the substrate core having a first side and a second side opposite the first side;
a first through via extending through the substrate core;
a first routing structure on the first side of the substrate core, wherein the first routing structure comprises first dielectric layers and first conductive features embedded in the first dielectric layers, wherein the first routing structure comprising comprises a first spiral routing stack, wherein the first spiral routing stack comprises:
a first conductive trace embedded in a first dielectric layer of the first dielectric layers, wherein the first conductive trace has a first semicircular shape or a first semi-polygonal shape in a top view;
a second conductive trace embedded in a second dielectric layer of the first dielectric layers, wherein the second dielectric layer is over the first dielectric layer, wherein the second conductive trace has a second semicircular shape or a second semi-polygonal shape in the top view;
and
a via embedded in the second dielectric layer and connecting the first conductive trace to the second conductive trace, wherein in the top view, the first conductive trace and the second conductive trace form a circular shape or a polygonal shape;
and
a second routing structure on the second side of the substrate core, the second routing structure comprising a second spiral routing stack, the second spiral routing stack being coupled to the first spiral routing stack through the first through via;
and
a first package component attached to the first routing structure of the package substrate.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/151,623Filed 9 Jan 2023 · us provisional application
Priority: 6 Sep 2022
Published: US 2024/0079356 A17 Mar 2024
Granted: 22 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10W 44/20
Electrical arrangements for controlling or matching impedance: at high-frequency [HF] or radio frequency [RF]
H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10W 42/20
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
H10W 70/05
Manufacture or treatment: of insulating or insulated package substrates, or of interposers, or of redistribution layers