Direct build-up layer on an encapsulated die package
AssigneeIntel Corporation
InventorsQing Ma, Chun Mu, Harry Fujimoto
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsQing Ma, Chun Mu, Harry Fujimoto
Estimating the term…
A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends vertically adjacent the microelectronic die active surface and vertically adjacent the encapsulation material surface.
A microelectronic package, comprising:
A method of fabricating a microelectronic package, comprising:
A method of fabricating a microelectronic package, comprising:
A method of fabricating a microelectronic package, comprising:
A method of fabricating a microelectronic package, comprising:
A method of fabricating a microelectronic package, comprising:
Dependencies are inferred from the claim text.