H10W 46/00
Marks applied to devices
Official title: Marks applied to devices, e.g. for alignment or identification
H10W46/00 (Marks applied to devices) appears on 7,004 US grants and 7,655 published applications in this corpus.
Search patents in H10W- Granted patents
- 7,004
- Published applications
- 7,655
- Assignees
- 1,298
- Inventors
- 12,740
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 4 | 0 |
| 1978 | 10 | 0 |
| 1979 | 2 | 0 |
| 1980 | 2 | 0 |
| 1981 | 6 | 0 |
| 1982 | 12 | 0 |
| 1983 | 10 | 0 |
| 1984 | 11 | 0 |
| 1985 | 8 | 0 |
| 1986 | 14 | 0 |
| 1987 | 10 | 0 |
| 1988 | 18 | 0 |
| 1989 | 12 | 0 |
| 1990 | 23 | 0 |
| 1991 | 28 | 0 |
| 1992 | 21 | 0 |
| 1993 | 23 | 0 |
| 1994 | 29 | 0 |
| 1995 | 40 | 0 |
| 1996 | 38 | 0 |
| 1997 | 44 | 0 |
| 1998 | 67 | 0 |
| 1999 | 116 | 0 |
| 2000 | 131 | 0 |
| 2001 | 136 | 66 |
| 2002 | 173 | 184 |
| 2003 | 181 | 211 |
| 2004 | 198 | 224 |
| 2005 | 154 | 239 |
| 2006 | 185 | 252 |
| 2007 | 142 | 245 |
| 2008 | 136 | 213 |
| 2009 | 141 | 215 |
| 2010 | 189 | 192 |
| 2011 | 197 | 227 |
| 2012 | 174 | 207 |
| 2013 | 227 | 244 |
| 2014 | 232 | 264 |
| 2015 | 298 | 350 |
| 2016 | 316 | 352 |
| 2017 | 332 | 404 |
| 2018 | 351 | 361 |
| 2019 | 342 | 429 |
| 2020 | 369 | 400 |
| 2021 | 357 | 438 |
| 2022 | 335 | 416 |
| 2023 | 303 | 462 |
| 2024 | 330 | 422 |
| 2025 | 328 | 390 |
| 2026 | 199 | 248 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H10W 46/301Marks applied to devices: for alignment2,853
- H10W 46/501Marks applied to devices: for use before dicing2,282
- H10W 46/601Marks applied to devices: for use after dicing2,138
- H10W 46/101Marks applied to devices: characterised by the type of information1,654
- H10W 46/401Marks applied to devices: for identification or tracking1,086
- H10W 46/201Located on the periphery of wafers383
Recent patents
- Method of manufacturing semiconductor device6 Oct 2026US 12,757,741 B2Samsung Electronics Co., Ltd.
- Memory device package having scribe line and method for manufacturing the same6 Oct 2026US 12,757,742 B2Nanya Technology Corporation
- Press pack power semiconductor device with locator strip6 Oct 2026US 12,757,743 B2Littelfuse, Inc.
- Semiconductor structure and alignment method thereof6 Oct 2026US 12,757,744 B2United Microelectronics Corp.
- Semiconductor package6 Oct 2026US 12,757,745 B2Samsung Electronics Co., Ltd.
- Lithography focus control method8 Oct 2026US 2026/0310070 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for Separating a Layer of Solid Material from a Workpiece8 Oct 2026US 2026/0314345 A1Siltectra GmbH
- Semiconductor package with stacked members8 Oct 2026US 2026/0314415 A1Samsung Electronics Co., Ltd.
- Method of manufacturing semiconductor device8 Oct 2026US 2026/0314430 A1SK hynix Inc.
- Assembly for sub-micron alignment and a method for sub-micron alignment using the assembly8 Oct 2026US 2026/0314431 A1National University of Singapore
Most cited
By later US patents
- Vertical gate all around (VGAA) devices and methods of manufacturing the same987US 9,536,738 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Method and apparatus for generating a device ID for stacked devices631US 7,111,149 B2Intel Corporation · 2006
- Semiconductor wafer edge marking561US 6,710,364 B2Texas Instruments Incorporated · 2004
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices528US 6,762,076 B2Intel Corporation · 2004