H10W 46/201
Located on the periphery of wafers
Official title: {located on the periphery of wafers, e.g. orientation notches or lot numbers}
H10W46/201 (Located on the periphery of wafers) appears on 383 US grants and 349 published applications in this corpus.
Search patents in H10W- Granted patents
- 383
- Published applications
- 349
- Assignees
- 178
- Inventors
- 864
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 5 | 0 |
| 1987 | 0 | 0 |
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 5 | 0 |
| 1992 | 5 | 0 |
| 1993 | 4 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 5 | 0 |
| 1997 | 4 | 0 |
| 1998 | 6 | 0 |
| 1999 | 14 | 0 |
| 2000 | 13 | 0 |
| 2001 | 16 | 5 |
| 2002 | 14 | 12 |
| 2003 | 9 | 11 |
| 2004 | 15 | 21 |
| 2005 | 11 | 14 |
| 2006 | 17 | 20 |
| 2007 | 13 | 18 |
| 2008 | 8 | 7 |
| 2009 | 5 | 9 |
| 2010 | 9 | 8 |
| 2011 | 5 | 6 |
| 2012 | 7 | 4 |
| 2013 | 6 | 13 |
| 2014 | 9 | 8 |
| 2015 | 12 | 18 |
| 2016 | 12 | 6 |
| 2017 | 18 | 20 |
| 2018 | 15 | 16 |
| 2019 | 10 | 24 |
| 2020 | 19 | 18 |
| 2021 | 14 | 17 |
| 2022 | 14 | 23 |
| 2023 | 7 | 14 |
| 2024 | 18 | 12 |
| 2025 | 11 | 17 |
| 2026 | 9 | 8 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device and wafer22 Sep 2026US 12,745,649 B2Sumitomo Electric Device Innovations, Inc.
- Indium phosphide substrate and method for producing indium phosphide substrate15 Sep 2026US 12,740,431 B2JX Advanced Metals Corporation
- Semiconductor device and method of fabricating the same4 Aug 2026US 12,701,798 B2Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
- Notched wafer and bonding support structure to improve wafer stacking5 May 2026US 12,622,303 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device manufacturing method with slip suppressing impurity region24 Feb 2026US 12,563,985 B2Fuji Electric Co., Ltd.
- Semiconductor package with stacked members8 Oct 2026US 2026/0314415 A1Samsung Electronics Co., Ltd.
- Package structure and method of manufacturing the same1 Oct 2026US 2026/0305211 A1Advanced Semiconductor Engineering, Inc.
- Semiconductor device13 Aug 2026US 2026/0239992 A1SK hynix Inc.
- Notched wafer and bonding support structure to improve wafer stacking13 Aug 2026US 2026/0240027 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor wafer, method for manufacturing semiconductor wafer, semiconductor chip, and method for manufacturing semiconductor chip28 May 2026US 2026/0150701 A1Mitsubishi Electric Corporation
Most cited
By later US patents
- Semiconductor wafer edge marking561US 6,710,364 B2Texas Instruments Incorporated · 2004
- Method for fabricating an SOI device in alignment with a device region formed in a semiconductor substrate268US 5,294,556 AFujitsu Limited · 1994
- Semiconductor wafer267US 6,864,534 B2Renesas Technology Corp. · 2005
- Semiconductor wafer marking for identification during processing119US 5,175,774 AMicron Technology, Inc. · 1992
- Integral semiconductor wafer map recording97US 5,256,578 AMotorola, Inc. · 1993