H10W 20/0696
By using sacrificial placeholders
Official title: {by using sacrificial placeholders, e.g. using sacrificial plugs}
H10W20/0696 (By using sacrificial placeholders) appears on 510 US grants and 776 published applications in this corpus.
Search patents in H10W- Granted patents
- 510
- Published applications
- 776
- Assignees
- 81
- Inventors
- 1,042
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 4 | 0 |
| 2000 | 7 | 0 |
| 2001 | 5 | 4 |
| 2002 | 2 | 2 |
| 2003 | 3 | 1 |
| 2004 | 1 | 1 |
| 2005 | 2 | 7 |
| 2006 | 5 | 6 |
| 2007 | 1 | 5 |
| 2008 | 3 | 5 |
| 2009 | 4 | 2 |
| 2010 | 2 | 3 |
| 2011 | 3 | 3 |
| 2012 | 3 | 6 |
| 2013 | 3 | 7 |
| 2014 | 6 | 3 |
| 2015 | 6 | 10 |
| 2016 | 13 | 14 |
| 2017 | 17 | 10 |
| 2018 | 11 | 20 |
| 2019 | 22 | 32 |
| 2020 | 37 | 39 |
| 2021 | 33 | 59 |
| 2022 | 50 | 100 |
| 2023 | 54 | 113 |
| 2024 | 70 | 139 |
| 2025 | 88 | 140 |
| 2026 | 51 | 45 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method of manufacturing FinFET devices with backside power rail and backside self-aligned via25 Aug 2026US 12,720,795 B2Taiwan Semiconductor Manfacturing Company, Ltd.
- Placeholder with dielectric liner protection to prevent direct backside contact (DBC) from shorting to gate25 Aug 2026US 12,720,853 B2International Business Machines Corporation
- Backside contact with full wrap-around contact18 Aug 2026US 12,713,673 B2International Business Machines Corporation
- Semiconductor devices including backside capacitors and methods of manufacture11 Aug 2026US 12,707,963 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device including extended backside contact structure4 Aug 2026US 12,701,768 B2Samsung Electronics Co., Ltd.
- Capacitance reduction for backside power rail device20 Aug 2026US 2026/0247653 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device and manufacturing method thereof13 Aug 2026US 2026/0239669 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structure and methods of forming the same13 Aug 2026US 2026/0239732 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Stacked device and method for forming vertical interconnect structure in stacked device using cyclic deposition and etching processes13 Aug 2026US 2026/0239938 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Backside memory integration6 Aug 2026US 2026/0231434 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Process for producing semiconductor integrated circuit device206US 7,553,756 B2Hitachi, Ltd. · 2009
- Complementary FETs with wrap around contacts and method of forming same124US 10,192,867 B1Globalfoundries Inc. · 2019
- Dual damascene structure80US 6,033,977 ASiemens Aktiengesellschaft · 2000
- Method of forming high aspect ratio structures for semiconductor devices75US 6,204,143 B1Micron Technology, Inc. · 2001
- Self-aligned wrap-around contacts for nanosheet devices66US 9,847,390 B1Globalfoundries Inc. · 2017