Stacked device and method for forming vertical interconnect structure in stacked device using cyclic deposition and etching processes

A method comprising:

• forming an isolation structure over a substrate;
• forming a first transistor and a second transistor over the isolation structure and the substrate, wherein the first transistor is between the second transistor and the isolation structure;
• forming a trench in gate structures of the first transistor and the second transistor and in the isolation structure;
• depositing a dielectric liner to line sidewalls and a bottom of the trench;
• depositing a conductive material in the trench and on the dielectric liner;
• etching the conductive material, wherein a top surface of the conductive material is lower than a top surface of the isolation structure after etching the conductive material;
• filling the trench with the conductive material;
• and
• performing a planarization process to remove the dielectric liner and the conductive material outside the trench.

A device comprising:

• a first channel structure and a second channel structure arranged along a first direction;
• a first gate structure covering the first channel structure and extending lengthwise along the first direction;
• a second gate structure covering the second channel structure and extending lengthwise along the first direction;
• a first source/drain structure and a second source/drain structure connected to the first channel structure and on opposite sides of the first gate structure;
• and
• an interconnect structure comprising:
• a dielectric liner interfacing the first gate structure and the second gate structure;
• and
• a conductive material in contact with the dielectric liner and electrically connected to the first source/drain structure and extending lengthwise along a second direction different from the first direction.