Complementary FETs with wrap around contacts and method of forming same

A method of forming a stacked integrated circuit structure comprising:

• forming a first FET on a substrate, the first FET including at least one first gate, at least one first source and at least one first drain;
• forming a spacer layer over the first source and the first drain of the first FET;
• forming a second FET over the spacer layer, the second FET being vertically stacked above the first FET, the second FET including at least one second gate, at least one second source and at least one second drain, the first and second gates being vertically aligned, and at least a portion of the second source and at least a portion of the second drain being above and vertically aligned with at least a portion of the first source and at least a portion of the first drain, respectively;
• forming a dielectric layer over the second FET;
• forming a first lateral conductive metal region and a first vertical conductive metal region, the first lateral conductive metal region surrounding at least one of the first source and the first drain of the first FET and extending laterally outward beyond any portion of the second FET thereabove, the first vertical conductive metal region extending upwards from the first lateral conductive metal region to a top surface of the dielectric layer;
• and
• forming a second vertical conductive metal region, the second vertical conductive metal region surrounding at least one of the second source and the second drain of the second FET and extending upwards to the top surface of the dielectric layer, the second vertical conductive metal region not intersecting the first vertical conductive metal region.