Semiconductor structure and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPei-Yu Chou, Ting Ying Wu, Meng-Ku Chen
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Abstract
A method includes forming nanostructures over a semiconductor substrate; forming a front-side interconnect structure over a front-side of the nanostructures; directly bonding a first side of a carrier substrate to the front-side interconnect structure using a dielectric-to-dielectric bonding process; depositing a dielectric layer on a second side of the carrier substrate; and forming a back-side interconnect structure over a back-side of the nanostructures. In an embodiment, the dielectric layer provides a tensile stress.
Claims20
A method comprising:
- forming a plurality of nanostructures over a semiconductor substrate;
- forming a front-side interconnect structure over a front-side of the plurality of nanostructures;
- directly bonding a first side of a carrier substrate to the front-side interconnect structure using a dielectric-to-dielectric bonding process;
- depositing a dielectric layer on a second side of the carrier substrate;
- and
- forming a back-side interconnect structure over a back-side of the plurality of nanostructures.
A method comprising:
- forming a plurality of stacking transistors on a first substrate;
- forming a first interconnect structure on the plurality of stacking transistors;
- depositing a first bonding layer on the first interconnect structure;
- forming a carrier structure comprising:
- depositing a second bonding layer on a second substrate;
- depositing an insulating layer on the second substrate opposite the second bonding layer, wherein the insulating layer exhibits tensile stress on the second substrate;
- after forming the carrier structure, bonding the second bonding layer to the first bonding layer using a direct bonding process;
- and
- after bonding the second bonding layer to the first bonding layer, forming a second interconnect structure on the plurality of stacking transistor opposite the first interconnect structure, wherein the second interconnect structure is electrically connected to the plurality of stacking transistors.
A device comprising:
- a stacking transistor;
- a first interconnect structure over and connected to a front-side of the stacking transistor;
- a second interconnect structure over and connected to a back-side of the stacking transistor;
- and
- a support structure attached to the first interconnect structure, wherein the support structure comprises a tensile stress layer on a support substrate.
Dependencies are inferred from the claim text.