Method of manufacturing FinFET devices with backside power rail and backside self-aligned via

A method comprising:

• providing a structure having an insulator, multiple fins on the insulator, a sacrificial gate structure engaging a channel region of a first fin of the fins, and gate spacers on opposing sidewalls of the sacrificial gate structure, wherein the first fin includes a first semiconductor layer over the insulator, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer;
• etching a source trench and a drain trench into the first fin adjacent the gate spacers, wherein the drain trench does not expose the second semiconductor layer, and wherein the source trench extends through the third semiconductor layer and the second semiconductor layer and into the first semiconductor layer;
• epitaxially growing a undoped silicon layer in the source trench and partially filling the source trench, wherein the undoped silicon layer extends from the first semiconductor layer to the third semiconductor layer;
• and
• epitaxially growing a source feature from the undoped silicon layer in the source trench and a drain feature from the third semiconductor layer in the drain trench.

A method comprising:

• providing a structure including a fin, wherein the fin includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer, wherein the first and the third semiconductor layers include a first semiconductor material, the second semiconductor layer includes a second semiconductor material that is different from the first semiconductor material;
• forming a sacrificial gate structure engaging a channel region of the fin;
• forming gate spacers on opposing sidewalls of the sacrificial gate structure;
• etching a source trench and a drain trench into the first fin adjacent the gate spacers, wherein the drain trench does not expose the second semiconductor layer, and wherein the source trench extends through the third semiconductor layer and the second semiconductor layer and into the first semiconductor layer;
• and
• epitaxially growing a fourth semiconductor layer in the source trench, wherein the fourth semiconductor layer partially fills the source trench, wherein the fourth semiconductor layer includes a semiconductor material that is different from the second semiconductor material.