Placeholder with dielectric liner protection to prevent direct backside contact (DBC) from shorting to gate
AssigneeInternational Business Machines Corporation
InventorsTsung-Sheng Kang, Tao Li, Ruilong Xie, Eric Miller
Life of this patent
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Abstract
A semiconductor structure includes a plurality of gate-all-around field effect transistors. Each of the gate-all-around field effect transistors includes first and second source-drain regions; at least one channel region interconnecting the first and second source-drain regions; and a gate structure surrounding the at least one channel region. A direct backside contact is located below one of the first and second source-drain regions. The direct backside contact has an upper portion. A dielectric liner is wrapped around the upper portion of the direct backside contact.
Claims16
A semiconductor structure comprising:
- a plurality of gate-all-around field effect transistors, each of the plurality of gate-all-around field effect transistors including:
- a first source-drain region and a second source-drain region;
- at least one channel region interconnecting the first source-drain region and the second source-drain region;
- and
- a gate structure surrounding the at least one channel region;
- a direct backside contact located below one of the first source-drain region and the second source-drain region, the direct backside contact having an upper portion;
- a dielectric liner wrapped around the upper portion of the direct backside contact;
- and
- a backside interlayer dielectric (BILD) below the plurality of gate-all-around field effect transistors, wherein a portion of the BILD comprises a protector BILD between the gate structure and the direct backside contact.
A semiconductor structure comprising:
- a plurality of gate-all-around field effect transistors, each of the plurality of gate-all-around field effect transistors including:
- a first source-drain region and a second source-drain region;
- at least one channel region interconnecting the first source-drain region and the second source-drain region;
- and
- a gate structure surrounding the at least one channel region;
- a direct backside contact located below one of the first source-drain region and the second source-drain region, the direct backside contact having an upper portion;
- a placeholder structure located below another one of the first source-drain region and the second source-drain region, the placeholder structure having an upper portion;
- a dielectric liner wrapped around the upper portion of the placeholder structure;
- and
- a backside interlayer dielectric (BILD) below the plurality of gate-all-around field effect transistors, wherein a portion of the BILD comprises a protector BILD between the gate structure and the direct backside contact.
Dependencies are inferred from the claim text.