Semiconductor devices including backside capacitors and methods of manufacture

A device comprising:

• a gate structure along at least three sides of a semiconductor channel region in a first cross-sectional view;
• a first source/drain region adjacent the gate structure and the semiconductor channel region in a second cross-sectional view that is perpendicular to the first cross-sectional view;
• a gate contact coupled to a surface of the gate structure, the gate contact extending from the surface of the gate structure along a first direction away from the semiconductor channel region;
• a first source/drain contact coupled to a surface of the first source/drain region, the first source/drain contact extending from the surface of the first source/drain region along a second direction away from the semiconductor channel region, the second direction being opposite the first direction;
• a first interconnect structure coupled to the first source/drain contact opposite the first source/drain region in the second direction;
• and
• a capacitor structure coupled to the first interconnect structure opposite the first source/drain contact in the second direction, wherein the capacitor structure is coupled to the first interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

A device comprising:

• a device layer comprising a transistor, wherein the transistor comprises:
• a stack of nanostructures;
• a gate structure surrounding the stack of nanostructures in a first cross-sectional view;
• and
• a source/drain region adjoining the stack of nanostructures in a second cross-sectional view that is perpendicular to the first cross-sectional view;
• a front-side interconnect structure on a front-side of the device layer, wherein the front-side interconnect structure includes a front-side source/drain contact electrically coupled to the source/drain region of the transistor, wherein the front-side source/drain contact extends along the gate structure of the transistor;
• a backside interconnect structure on a backside of the device layer, the backside interconnect structure comprising:
• a backside conductive line that is electrically coupled to the source/drain region of the transistor by a backside source/drain contact, wherein the front-side source/drain contact and the backside source/drain contact are on opposing sides of the source/drain region;
• a first insulating layer;
• and
• a first bond pad in the first insulating layer;
• a first capacitor structure bonded to the backside interconnect structure, the first capacitor structure comprising:
• a capacitor;
• a second insulating layer contacting the first insulating layer;
• and
• a second bond pad contacting the first bond pad.